JPS57114927A - Controlling transmitter - Google Patents
Controlling transmitterInfo
- Publication number
- JPS57114927A JPS57114927A JP84781A JP84781A JPS57114927A JP S57114927 A JPS57114927 A JP S57114927A JP 84781 A JP84781 A JP 84781A JP 84781 A JP84781 A JP 84781A JP S57114927 A JPS57114927 A JP S57114927A
- Authority
- JP
- Japan
- Prior art keywords
- line
- lines
- data
- main body
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
PURPOSE:To enable to assign the same frequency to a transmission and reception circuit, by providing transmission data lines and reception data lines in separation, in a multi-frequency data bus provided amoung a control device main body and a plurality of process controllers. CONSTITUTION:A control device main body 1 is connected to an address line AL, reception data line RL, and transmission data line TL of a data bus DB, an operation controller 2 is connected to the lines AL, RL, TL, and process controllers 3a, 3b are connected to the lines AL, TL, and AL, RL respectively. For example, the device 3a outputs a process data to the line TL and a device key address to the line AL. The main body 1 makes operation processing based on the process data and the result is outputted to the line RL. The device 3b is received from the lines AL, RL for a specified operation. The device 2 also receives from the lines AL, RL for the operation instructed by the main body 1. In this case, the device 2 makes transmission of an answer back data to the main body 1 via the line TL.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP84781A JPS57114927A (en) | 1981-01-07 | 1981-01-07 | Controlling transmitter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP84781A JPS57114927A (en) | 1981-01-07 | 1981-01-07 | Controlling transmitter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57114927A true JPS57114927A (en) | 1982-07-17 |
Family
ID=11485024
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP84781A Pending JPS57114927A (en) | 1981-01-07 | 1981-01-07 | Controlling transmitter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57114927A (en) |
-
1981
- 1981-01-07 JP JP84781A patent/JPS57114927A/en active Pending
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