JPS57114904A - Sequence controlling system - Google Patents

Sequence controlling system

Info

Publication number
JPS57114904A
JPS57114904A JP135981A JP135981A JPS57114904A JP S57114904 A JPS57114904 A JP S57114904A JP 135981 A JP135981 A JP 135981A JP 135981 A JP135981 A JP 135981A JP S57114904 A JPS57114904 A JP S57114904A
Authority
JP
Japan
Prior art keywords
level
signals
signal
subprogram
ffs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP135981A
Other languages
Japanese (ja)
Inventor
Kazuo Imayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP135981A priority Critical patent/JPS57114904A/en
Publication of JPS57114904A publication Critical patent/JPS57114904A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Feedback Control In General (AREA)

Abstract

PURPOSE:To achieve an effective program, by decreasing time loss accompanied with the increase in a main program, through the selection of a control program of an object to be controlled processed next for the preparation of a subprogram. CONSTITUTION:A controller 12 transmits a selection signal E by detecting signals A1, A3 both at H level. This signal E is applied to each clock terminal of FFs B1-Bn. Output signals C1, C3 of the FFs B1, B3 are at H level. The level of the signals C1, C3 is applied to the controller 12 via the common bus 11. The device 12 recognizes the signals C1, C3 at H level and prepares a microprogram step being a subprogram instructed with the combination of logical level of signals C1-Cn in advance, and starts scanning detecting the operation instructing signal. The device 12 executes programs for control of the object to be controlled in the said microprogram.
JP135981A 1981-01-08 1981-01-08 Sequence controlling system Pending JPS57114904A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP135981A JPS57114904A (en) 1981-01-08 1981-01-08 Sequence controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP135981A JPS57114904A (en) 1981-01-08 1981-01-08 Sequence controlling system

Publications (1)

Publication Number Publication Date
JPS57114904A true JPS57114904A (en) 1982-07-17

Family

ID=11499296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP135981A Pending JPS57114904A (en) 1981-01-08 1981-01-08 Sequence controlling system

Country Status (1)

Country Link
JP (1) JPS57114904A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154503A (en) * 1983-02-23 1984-09-03 Toshiba Corp Process controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154503A (en) * 1983-02-23 1984-09-03 Toshiba Corp Process controller

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