JPS57113237A - Recognition device - Google Patents

Recognition device

Info

Publication number
JPS57113237A
JPS57113237A JP55189542A JP18954280A JPS57113237A JP S57113237 A JPS57113237 A JP S57113237A JP 55189542 A JP55189542 A JP 55189542A JP 18954280 A JP18954280 A JP 18954280A JP S57113237 A JPS57113237 A JP S57113237A
Authority
JP
Japan
Prior art keywords
data
binary signal
circuit
signal
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55189542A
Other languages
Japanese (ja)
Inventor
Masahito Nakajima
Tetsuo Hizuka
Yushi Inagaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55189542A priority Critical patent/JPS57113237A/en
Publication of JPS57113237A publication Critical patent/JPS57113237A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]

Abstract

PURPOSE:To detect an insufficient image as improper wiring by converting a reference wiring pattern video signal into binary signal, storing the enlarged image as a reference data in a memory, and comparing the read data with the data of input image. CONSTITUTION:An image pickup device 6 picks up a semiconductor chip 5 on an X-Y stage 1 in an automatic wire bonder. A pretreating circuit 7 converts a video signal from the device 6 into a binary signal and increases the thickness of the line. A memory 10 stores the enlarged image data of the reference wiring pattern converted to binary signal and increased in the thickness of the line from the circuit 7. A pattern data comparator 8 compares the input image data relative to the recognition pattern with the enlarged image data, and the comparison signal is outputted to an output device 12. A control circuit 11 controls the entire system. In this manner, improper warning cycle can be extremely shortened.
JP55189542A 1980-12-30 1980-12-30 Recognition device Pending JPS57113237A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55189542A JPS57113237A (en) 1980-12-30 1980-12-30 Recognition device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55189542A JPS57113237A (en) 1980-12-30 1980-12-30 Recognition device

Publications (1)

Publication Number Publication Date
JPS57113237A true JPS57113237A (en) 1982-07-14

Family

ID=16243047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55189542A Pending JPS57113237A (en) 1980-12-30 1980-12-30 Recognition device

Country Status (1)

Country Link
JP (1) JPS57113237A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5935892A (en) * 1982-08-20 1984-02-27 Nec Corp Laser working device
JPS59121563A (en) * 1982-12-28 1984-07-13 Fujitsu Ltd Device for correcting design data of integrated circuit
JPS59123983A (en) * 1982-12-29 1984-07-17 Fujitsu Ltd Pattern checking device
JPS59220883A (en) * 1983-05-30 1984-12-12 Hitachi Ltd Repeated pattern checking device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5935892A (en) * 1982-08-20 1984-02-27 Nec Corp Laser working device
JPS59121563A (en) * 1982-12-28 1984-07-13 Fujitsu Ltd Device for correcting design data of integrated circuit
JPS59123983A (en) * 1982-12-29 1984-07-17 Fujitsu Ltd Pattern checking device
JPS59220883A (en) * 1983-05-30 1984-12-12 Hitachi Ltd Repeated pattern checking device

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