JPS57111866A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS57111866A
JPS57111866A JP18779880A JP18779880A JPS57111866A JP S57111866 A JPS57111866 A JP S57111866A JP 18779880 A JP18779880 A JP 18779880A JP 18779880 A JP18779880 A JP 18779880A JP S57111866 A JPS57111866 A JP S57111866A
Authority
JP
Japan
Prior art keywords
signal
memory
supplied
address signal
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18779880A
Other languages
Japanese (ja)
Other versions
JPS6052462B2 (en
Inventor
Tsutomu Yanagisawa
Sasae Kurimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18779880A priority Critical patent/JPS6052462B2/en
Publication of JPS57111866A publication Critical patent/JPS57111866A/en
Publication of JPS6052462B2 publication Critical patent/JPS6052462B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Storage Device Security (AREA)

Abstract

PURPOSE:To protect the data stored in a memory and to realize a small and simple constitution of a memory, by securing an access of a prescribed byte number to a specific memory after writing a prescribed data into a prescribed circuit. CONSTITUTION:When a main memory MM and a specific memory SM are read, an address signal to receive an access is supplied to an address signal line AL. A decoder DC decodes the address signal to give the rise to the chip selection signal of a chip selection line CSO or CSI during the supply of the address signal. When a data is written into the memory SM, an address signal corresponding to the address allotted to an allowable period setting circuit is first supplied to the line AL. At the same time, the mode signal supplied to a mode signal line RWO is defined as the writing mode level. The decoder DC decodes the mode signal to give the rise to the signal which is supplied onto a selection line SL of the allowable period setting circuit.
JP18779880A 1980-12-29 1980-12-29 Memory control method Expired JPS6052462B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18779880A JPS6052462B2 (en) 1980-12-29 1980-12-29 Memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18779880A JPS6052462B2 (en) 1980-12-29 1980-12-29 Memory control method

Publications (2)

Publication Number Publication Date
JPS57111866A true JPS57111866A (en) 1982-07-12
JPS6052462B2 JPS6052462B2 (en) 1985-11-19

Family

ID=16212411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18779880A Expired JPS6052462B2 (en) 1980-12-29 1980-12-29 Memory control method

Country Status (1)

Country Link
JP (1) JPS6052462B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413652A (en) * 1987-07-07 1989-01-18 Nec Corp Single chip microcomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413652A (en) * 1987-07-07 1989-01-18 Nec Corp Single chip microcomputer

Also Published As

Publication number Publication date
JPS6052462B2 (en) 1985-11-19

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