JPS57111815A - Decoding system of binary code - Google Patents
Decoding system of binary codeInfo
- Publication number
- JPS57111815A JPS57111815A JP18830480A JP18830480A JPS57111815A JP S57111815 A JPS57111815 A JP S57111815A JP 18830480 A JP18830480 A JP 18830480A JP 18830480 A JP18830480 A JP 18830480A JP S57111815 A JPS57111815 A JP S57111815A
- Authority
- JP
- Japan
- Prior art keywords
- data
- bits
- bit
- output
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
- G11B2020/1461—8 to 14 modulation, e.g. the EFM code used on CDs or mini-discs
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18830480A JPS57111815A (en) | 1980-12-27 | 1980-12-27 | Decoding system of binary code |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18830480A JPS57111815A (en) | 1980-12-27 | 1980-12-27 | Decoding system of binary code |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57111815A true JPS57111815A (en) | 1982-07-12 |
JPS6334546B2 JPS6334546B2 (ja) | 1988-07-11 |
Family
ID=16221263
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18830480A Granted JPS57111815A (en) | 1980-12-27 | 1980-12-27 | Decoding system of binary code |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57111815A (ja) |
-
1980
- 1980-12-27 JP JP18830480A patent/JPS57111815A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6334546B2 (ja) | 1988-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB2183971B (en) | Data transmission system | |
HK88394A (en) | Method of transmitting information, encoding device for use in the method, and decoding device for use in the method | |
JPS57176866A (en) | Encoder of binary signal | |
EP1014589A3 (en) | A variable length codeword decoder | |
CA2019821A1 (en) | Signal conversion circuit | |
JPS5625849A (en) | Coding system | |
JPS57111815A (en) | Decoding system of binary code | |
JPS57112158A (en) | Code converting circuit | |
JPS5483411A (en) | Binary data coding system | |
JPS5710566A (en) | Decoding circuit | |
JPS56117423A (en) | Binary coding circuit by multistage threshold level | |
JPS5696553A (en) | Code conversion circuit | |
JPS55120280A (en) | Selection type cross conversion system | |
JPS54130111A (en) | Coding system | |
JPS57140070A (en) | Decoder for picture signal | |
JPS57154612A (en) | Digital modulating and demodulating system | |
JPS5683163A (en) | Encoding system | |
JPS54122022A (en) | Decoding circuit | |
JPS5780850A (en) | Decoding system for modified huffman code | |
JPS57188158A (en) | Parity bit addition circuit | |
JPS5731240A (en) | Decoder | |
ES473132A1 (es) | Un convertidor digital-a-analogico utilizado codificador-de-codificador micc (modulacion por impulsos codificados) para codificar y decodificar | |
JPS5754455A (en) | Code transmission system | |
JPS5369017A (en) | Binary data coding system | |
JPS55133158A (en) | Pulse code communication system |