JPS57108915A - Common-use exclusive control system - Google Patents

Common-use exclusive control system

Info

Publication number
JPS57108915A
JPS57108915A JP55183714A JP18371480A JPS57108915A JP S57108915 A JPS57108915 A JP S57108915A JP 55183714 A JP55183714 A JP 55183714A JP 18371480 A JP18371480 A JP 18371480A JP S57108915 A JPS57108915 A JP S57108915A
Authority
JP
Japan
Prior art keywords
state
input
queue
output request
volume
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55183714A
Other languages
Japanese (ja)
Inventor
Hajime Sugiura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55183714A priority Critical patent/JPS57108915A/en
Publication of JPS57108915A publication Critical patent/JPS57108915A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

PURPOSE:To reset a deadlock state by releasing the volume that a system occupies only when it is judged that a control program has a dead lock possibly. CONSTITUTION:When volumes 7a, 7b,... are in a stateIfor an input and output request issued by a host through one channel 3, the input and output request is executed and when in a state II, a busy state is reported to form a queue. When they are in a state III or IV, the presence of another volume which is occupied or in exclusive use from a corresponding channel and the presence of a queue showing an input and output request group to a corresponding volume are checked. When the queue is formed, a busy plus attention status is reported to give information on the possibility of a deadlock.
JP55183714A 1980-12-26 1980-12-26 Common-use exclusive control system Pending JPS57108915A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55183714A JPS57108915A (en) 1980-12-26 1980-12-26 Common-use exclusive control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55183714A JPS57108915A (en) 1980-12-26 1980-12-26 Common-use exclusive control system

Publications (1)

Publication Number Publication Date
JPS57108915A true JPS57108915A (en) 1982-07-07

Family

ID=16140665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55183714A Pending JPS57108915A (en) 1980-12-26 1980-12-26 Common-use exclusive control system

Country Status (1)

Country Link
JP (1) JPS57108915A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5977563A (en) * 1982-10-26 1984-05-04 Nec Corp File control processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5977563A (en) * 1982-10-26 1984-05-04 Nec Corp File control processor

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