JPS56153470A - Multiple computer system - Google Patents

Multiple computer system

Info

Publication number
JPS56153470A
JPS56153470A JP5653780A JP5653780A JPS56153470A JP S56153470 A JPS56153470 A JP S56153470A JP 5653780 A JP5653780 A JP 5653780A JP 5653780 A JP5653780 A JP 5653780A JP S56153470 A JPS56153470 A JP S56153470A
Authority
JP
Japan
Prior art keywords
program
data
computer
processing
queuing table
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5653780A
Other languages
Japanese (ja)
Inventor
Hitoshi Amano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5653780A priority Critical patent/JPS56153470A/en
Publication of JPS56153470A publication Critical patent/JPS56153470A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Abstract

PURPOSE:To improve the efficiency of each computer, by providing a queuing table on the common memory in the mutliple computer system provided with plural computers. CONSTITUTION:Processing program 4 of computer A generates data 5 and starts program 6 and transfers information concerning data 5 to program A. Program A registers information concerning data 5 and data 5 itself in queuing table 10 of common memory 3 and starts program 7 of computer B. Program 7 takes out the processing request which is registered in the beginning of queuing table 10, and program 7 performs writing to data 8 and starts processing program 9 as required. Program 7 erases information concerning data 8 from queuing table 10 when writing to data 8 is completed, and this operation is repeated until processing requests registered in queuing table 10 are executed, and processing results of processing program 9 are operated similarly through queue table 11 if it is necessary to send them to computer A.
JP5653780A 1980-04-28 1980-04-28 Multiple computer system Pending JPS56153470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5653780A JPS56153470A (en) 1980-04-28 1980-04-28 Multiple computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5653780A JPS56153470A (en) 1980-04-28 1980-04-28 Multiple computer system

Publications (1)

Publication Number Publication Date
JPS56153470A true JPS56153470A (en) 1981-11-27

Family

ID=13029828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5653780A Pending JPS56153470A (en) 1980-04-28 1980-04-28 Multiple computer system

Country Status (1)

Country Link
JP (1) JPS56153470A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60129835A (en) * 1983-12-16 1985-07-11 Fujitsu Ltd Instruction controlling system
JPH01276640A (en) * 1988-04-28 1989-11-07 Fujitsu Ltd Alignment of wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60129835A (en) * 1983-12-16 1985-07-11 Fujitsu Ltd Instruction controlling system
JPH01276640A (en) * 1988-04-28 1989-11-07 Fujitsu Ltd Alignment of wafer

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