JPS57107035A - Drawing system by electron ray - Google Patents

Drawing system by electron ray

Info

Publication number
JPS57107035A
JPS57107035A JP18483580A JP18483580A JPS57107035A JP S57107035 A JPS57107035 A JP S57107035A JP 18483580 A JP18483580 A JP 18483580A JP 18483580 A JP18483580 A JP 18483580A JP S57107035 A JPS57107035 A JP S57107035A
Authority
JP
Japan
Prior art keywords
sample
chip
output
eos
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18483580A
Other languages
Japanese (ja)
Other versions
JPH0320894B2 (en
Inventor
Katsuji Tanaka
Takamasa Wakasugi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shibaura Machine Co Ltd
Original Assignee
Toshiba Machine Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Machine Co Ltd filed Critical Toshiba Machine Co Ltd
Priority to JP18483580A priority Critical patent/JPS57107035A/en
Publication of JPS57107035A publication Critical patent/JPS57107035A/en
Publication of JPH0320894B2 publication Critical patent/JPH0320894B2/ja
Granted legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3174—Particle-beam lithography, e.g. electron beam lithography

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Analytical Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE:To suppress a chip interval to a necessary minimum value by a method wherein a mask is provided on a sample when the sample is divided into a unit chip and a drawing operation starts when a drawing start position along an X-Y axis direction of each chip coincides with X-Y of a scaling value previously calculated. CONSTITUTION:When a sample is divided into a multiplicity of chips, a mask is mounted on the sample, wherein a scaling value X-Y concerned with shifting of a table has been given beforehand. Subsequently, a figure data corresponding to the scaling values X-Y being coded is stored in a storage file 21 and the data is supplied sequentially to CPU22 including a drawing control program and a memory. Subsequently, the output is delivered to a drawing data output portion 23 including a buffer, a dot convertion logic or the like, and then the output is successively outputted to a blanking circuit EOS, and the circuit EOS is controlled by utilizing a laser measuring equipment 24 for detecting a position along X-Y direction of a sample stand, a present position counter 25 and a synchronous control 26.
JP18483580A 1980-12-25 1980-12-25 Drawing system by electron ray Granted JPS57107035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18483580A JPS57107035A (en) 1980-12-25 1980-12-25 Drawing system by electron ray

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18483580A JPS57107035A (en) 1980-12-25 1980-12-25 Drawing system by electron ray

Publications (2)

Publication Number Publication Date
JPS57107035A true JPS57107035A (en) 1982-07-03
JPH0320894B2 JPH0320894B2 (en) 1991-03-20

Family

ID=16160133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18483580A Granted JPS57107035A (en) 1980-12-25 1980-12-25 Drawing system by electron ray

Country Status (1)

Country Link
JP (1) JPS57107035A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58223324A (en) * 1982-06-21 1983-12-24 Toshiba Corp Drawing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58223324A (en) * 1982-06-21 1983-12-24 Toshiba Corp Drawing device
JPH0544171B2 (en) * 1982-06-21 1993-07-05 Tokyo Shibaura Electric Co

Also Published As

Publication number Publication date
JPH0320894B2 (en) 1991-03-20

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