JPS5588133A - Screen memory control system - Google Patents

Screen memory control system

Info

Publication number
JPS5588133A
JPS5588133A JP16274478A JP16274478A JPS5588133A JP S5588133 A JPS5588133 A JP S5588133A JP 16274478 A JP16274478 A JP 16274478A JP 16274478 A JP16274478 A JP 16274478A JP S5588133 A JPS5588133 A JP S5588133A
Authority
JP
Japan
Prior art keywords
information
line
screen
stored
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16274478A
Other languages
Japanese (ja)
Inventor
Shogo Takayama
Minoru Ootsuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16274478A priority Critical patent/JPS5588133A/en
Publication of JPS5588133A publication Critical patent/JPS5588133A/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To eliminate the need to store information for one screen continuously in a screen memory for a CRT display unit, by sectioning information pieces for one line of a display part and then by appending an initial address of a following line to the head of each line.
CONSTITUTION: In RAM memory 2, screen information DT of each line to be displayed on CRT display part 4 is stored together with next link address NAR as line information LD, and address NAR is the initial address of line information LD of stored screen information of a following line. To display information, the initial address of information DT1 of the 1st line is entered from microprocessor 1 into register 7 and character codes are read out one after another from memory 2 and stored in buffer memory 10. lastly, until address NAR is read out and registered in register 5 and screen information DT2 of a following line is stored in buffer memory 11, information in buffer memory 10 is converted by character generator 14 into a pattern signal, which is displayed on the CRT display part.
COPYRIGHT: (C)1980,JPO&Japio
JP16274478A 1978-12-27 1978-12-27 Screen memory control system Pending JPS5588133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16274478A JPS5588133A (en) 1978-12-27 1978-12-27 Screen memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16274478A JPS5588133A (en) 1978-12-27 1978-12-27 Screen memory control system

Publications (1)

Publication Number Publication Date
JPS5588133A true JPS5588133A (en) 1980-07-03

Family

ID=15760427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16274478A Pending JPS5588133A (en) 1978-12-27 1978-12-27 Screen memory control system

Country Status (1)

Country Link
JP (1) JPS5588133A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59174886A (en) * 1983-03-25 1984-10-03 株式会社東芝 Display controller
JP2001154652A (en) * 1999-11-30 2001-06-08 Sanyo Electric Co Ltd Display controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59174886A (en) * 1983-03-25 1984-10-03 株式会社東芝 Display controller
JP2001154652A (en) * 1999-11-30 2001-06-08 Sanyo Electric Co Ltd Display controller

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