JPS5691564A - Test system of communication controller - Google Patents

Test system of communication controller

Info

Publication number
JPS5691564A
JPS5691564A JP16902479A JP16902479A JPS5691564A JP S5691564 A JPS5691564 A JP S5691564A JP 16902479 A JP16902479 A JP 16902479A JP 16902479 A JP16902479 A JP 16902479A JP S5691564 A JPS5691564 A JP S5691564A
Authority
JP
Japan
Prior art keywords
signal
circuit
reset
turns
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16902479A
Other languages
Japanese (ja)
Inventor
Yoshihisa Ogawa
Yuuji Sadakuni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16902479A priority Critical patent/JPS5691564A/en
Publication of JPS5691564A publication Critical patent/JPS5691564A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer And Data Communications (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To shorten the test time of a communication controller by enabling it to test itself when a circuit control circuit is reset, not only by supplying a reset signal to the circuit control circuit, but also by operating the control circuit to discriminate its normalcy. CONSTITUTION:With a reset indication, FF5 turns on to reset the circuit. Next, the turning off of a data set ready DR and ready-for-sending CS signal is confirmed and then a data terminal ready ER and request-to-send RS signal is turned on to discriminate whether the DR and CS signal turns on a certain time later. After the DR and CS signal turns on, the ER and RS signal is turned off and further whether the DR and CS signal turns off a certain time later is discriminated. When the DR and CS signal is off, circuit scanning register 2 advances and said operation is performed repeatedly. When the said operation on the final circuit ends, reset indication FF5 is turned off and the self-testing operation is completed.
JP16902479A 1979-12-25 1979-12-25 Test system of communication controller Pending JPS5691564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16902479A JPS5691564A (en) 1979-12-25 1979-12-25 Test system of communication controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16902479A JPS5691564A (en) 1979-12-25 1979-12-25 Test system of communication controller

Publications (1)

Publication Number Publication Date
JPS5691564A true JPS5691564A (en) 1981-07-24

Family

ID=15878905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16902479A Pending JPS5691564A (en) 1979-12-25 1979-12-25 Test system of communication controller

Country Status (1)

Country Link
JP (1) JPS5691564A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60105338A (en) * 1983-11-12 1985-06-10 Fujitsu Ltd Line ciphering device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60105338A (en) * 1983-11-12 1985-06-10 Fujitsu Ltd Line ciphering device

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