JPS5689147A - Frame sunchronizing system - Google Patents

Frame sunchronizing system

Info

Publication number
JPS5689147A
JPS5689147A JP16722879A JP16722879A JPS5689147A JP S5689147 A JPS5689147 A JP S5689147A JP 16722879 A JP16722879 A JP 16722879A JP 16722879 A JP16722879 A JP 16722879A JP S5689147 A JPS5689147 A JP S5689147A
Authority
JP
Japan
Prior art keywords
time
synchronization
hunting
circuit
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16722879A
Other languages
Japanese (ja)
Inventor
Hisanobu Fujimoto
Takeo Fukushima
Masami Mizuguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16722879A priority Critical patent/JPS5689147A/en
Publication of JPS5689147A publication Critical patent/JPS5689147A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To make it possible that the system escapes from false synchronization, by hunting forcedly frame synchronization again when multiframe synchronization is not led in for a prescribed time after the establishment time of main frame synchronization. CONSTITUTION:The system enters to false synchronization at time (3). The re- hunting circuit which is a delay switching circuit is set at time (3). After fixed time T, the re-hunting circuit outputs a clear pulse to erase contents of the 5-bit register. Here, time T is selected longer than the time between signal frame synchronization leading-in times (5)-(7). As a result, hunting of the terminal station frame synchronous circuit is caused forcedly, and the system is escaped from false synchronization.
JP16722879A 1979-12-22 1979-12-22 Frame sunchronizing system Pending JPS5689147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16722879A JPS5689147A (en) 1979-12-22 1979-12-22 Frame sunchronizing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16722879A JPS5689147A (en) 1979-12-22 1979-12-22 Frame sunchronizing system

Publications (1)

Publication Number Publication Date
JPS5689147A true JPS5689147A (en) 1981-07-20

Family

ID=15845817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16722879A Pending JPS5689147A (en) 1979-12-22 1979-12-22 Frame sunchronizing system

Country Status (1)

Country Link
JP (1) JPS5689147A (en)

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