JPS53128902A - Correction circuit for time distortion - Google Patents

Correction circuit for time distortion

Info

Publication number
JPS53128902A
JPS53128902A JP4356977A JP4356977A JPS53128902A JP S53128902 A JPS53128902 A JP S53128902A JP 4356977 A JP4356977 A JP 4356977A JP 4356977 A JP4356977 A JP 4356977A JP S53128902 A JPS53128902 A JP S53128902A
Authority
JP
Japan
Prior art keywords
correction circuit
signal
time distortion
minus
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4356977A
Other languages
Japanese (ja)
Inventor
Kozo Kamata
Tomihisa Nishijima
Morihito Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4356977A priority Critical patent/JPS53128902A/en
Publication of JPS53128902A publication Critical patent/JPS53128902A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/20—Repeater circuits; Relay circuits
    • H04L25/24—Relay circuits using discharge tubes or semiconductor devices

Abstract

PURPOSE:To prevent the jitter occurrence for the receiving circuit of the doublecurrent signal by holding the signal arriving the ''minus'' region when the signal is once received until the next signal arrives to reach the ''minus(plus)'' region.
JP4356977A 1977-04-18 1977-04-18 Correction circuit for time distortion Pending JPS53128902A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4356977A JPS53128902A (en) 1977-04-18 1977-04-18 Correction circuit for time distortion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4356977A JPS53128902A (en) 1977-04-18 1977-04-18 Correction circuit for time distortion

Publications (1)

Publication Number Publication Date
JPS53128902A true JPS53128902A (en) 1978-11-10

Family

ID=12667368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4356977A Pending JPS53128902A (en) 1977-04-18 1977-04-18 Correction circuit for time distortion

Country Status (1)

Country Link
JP (1) JPS53128902A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019053579A (en) * 2017-09-15 2019-04-04 ラピスセミコンダクタ株式会社 Battery monitoring device and battery monitoring system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019053579A (en) * 2017-09-15 2019-04-04 ラピスセミコンダクタ株式会社 Battery monitoring device and battery monitoring system

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