JPS5684084A - Reception state detector - Google Patents

Reception state detector

Info

Publication number
JPS5684084A
JPS5684084A JP16179079A JP16179079A JPS5684084A JP S5684084 A JPS5684084 A JP S5684084A JP 16179079 A JP16179079 A JP 16179079A JP 16179079 A JP16179079 A JP 16179079A JP S5684084 A JPS5684084 A JP S5684084A
Authority
JP
Japan
Prior art keywords
circuit
bit
signal
generates
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16179079A
Other languages
Japanese (ja)
Other versions
JPS6332316B2 (en
Inventor
Masayoshi Hirashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16179079A priority Critical patent/JPS5684084A/en
Publication of JPS5684084A publication Critical patent/JPS5684084A/en
Publication of JPS6332316B2 publication Critical patent/JPS6332316B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/025—Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame
    • H04N7/035—Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)

Abstract

PURPOSE:To detect and display a reception rate easily and accurately by generating the same signal as a transmitted prescribed pseudo-random signal at a reception side, by making a bit-to-bit comparison between the both and by counting mumber in dissidence. CONSTITUTION:Clock generating circuit 19 generates a clock pulse synchronizing with a received signal. Clock gate circuit 21 receives the clock pulse from circuit 19 and outputs a 256-bit clock pulse as a gate pulse while binary information is superposed at the 20th H. Further, gate pulse generating circuit 22 generates gate pulses in the 1st 16-bit and following 240-bit periods of the above-mentioned binary information signal. The received signal, on the other hand, is delayed and sampled by delay sampling circuit 20, whose output is supplied to comparison signal generating circuit 23. Circuit 23 generates a comparison PN code signal from outputs of circuits 20-22. Comparing circuit 24 compares signals of circuits 20 and 23 with each other, bit by bit, and when both the signals disagree, generates a dissidence detection signal. This output is counted by counting circuit 25, whose count value is displayed 26.
JP16179079A 1979-12-12 1979-12-12 Reception state detector Granted JPS5684084A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16179079A JPS5684084A (en) 1979-12-12 1979-12-12 Reception state detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16179079A JPS5684084A (en) 1979-12-12 1979-12-12 Reception state detector

Publications (2)

Publication Number Publication Date
JPS5684084A true JPS5684084A (en) 1981-07-09
JPS6332316B2 JPS6332316B2 (en) 1988-06-29

Family

ID=15741950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16179079A Granted JPS5684084A (en) 1979-12-12 1979-12-12 Reception state detector

Country Status (1)

Country Link
JP (1) JPS5684084A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5068407A (en) * 1973-10-19 1975-06-07
JPS51134008A (en) * 1975-05-15 1976-11-20 Nec Corp Error measurement circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5068407A (en) * 1973-10-19 1975-06-07
JPS51134008A (en) * 1975-05-15 1976-11-20 Nec Corp Error measurement circuit

Also Published As

Publication number Publication date
JPS6332316B2 (en) 1988-06-29

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