JPS5680887A - Electric charge transfer memory device - Google Patents

Electric charge transfer memory device

Info

Publication number
JPS5680887A
JPS5680887A JP15563479A JP15563479A JPS5680887A JP S5680887 A JPS5680887 A JP S5680887A JP 15563479 A JP15563479 A JP 15563479A JP 15563479 A JP15563479 A JP 15563479A JP S5680887 A JPS5680887 A JP S5680887A
Authority
JP
Japan
Prior art keywords
register
series
information
memory information
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15563479A
Other languages
Japanese (ja)
Inventor
Takashi Oba
Kenji Taniguchi
Tominobu Yamamoto
Yoshitaka Kitano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP15563479A priority Critical patent/JPS5680887A/en
Publication of JPS5680887A publication Critical patent/JPS5680887A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make possible the reading and writing of the memory information normally as an external characteristic in the case of the defect being present in the parallel register by converting an address signal showing the register including defect into an address signal showing other register.
CONSTITUTION: A series memory information is fed to a series register 1 through an input line 5, transferred successively in a register 1 by a clock, and when the memory place is filled, the respective memory information of the register 1 is transferred to the corresponding parallel registers P0WP63 by a timing signal. When the respective parallel register is full of the information and the information is filled in the register 1, the memory information located at the lowermost line of the respective parallel register is moved simultaneously to the series register 2 by a series transfer clock signal, and thereafter output in series by the clock signal.
COPYRIGHT: (C)1981,JPO&Japio
JP15563479A 1979-12-03 1979-12-03 Electric charge transfer memory device Pending JPS5680887A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15563479A JPS5680887A (en) 1979-12-03 1979-12-03 Electric charge transfer memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15563479A JPS5680887A (en) 1979-12-03 1979-12-03 Electric charge transfer memory device

Publications (1)

Publication Number Publication Date
JPS5680887A true JPS5680887A (en) 1981-07-02

Family

ID=15610261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15563479A Pending JPS5680887A (en) 1979-12-03 1979-12-03 Electric charge transfer memory device

Country Status (1)

Country Link
JP (1) JPS5680887A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59229779A (en) * 1983-05-06 1984-12-24 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Series-parallel-series type integrated memory circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59229779A (en) * 1983-05-06 1984-12-24 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Series-parallel-series type integrated memory circuit

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