JPS5680705A - Controller - Google Patents

Controller

Info

Publication number
JPS5680705A
JPS5680705A JP15838679A JP15838679A JPS5680705A JP S5680705 A JPS5680705 A JP S5680705A JP 15838679 A JP15838679 A JP 15838679A JP 15838679 A JP15838679 A JP 15838679A JP S5680705 A JPS5680705 A JP S5680705A
Authority
JP
Japan
Prior art keywords
output
external device
pulse
controller
routine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15838679A
Other languages
Japanese (ja)
Inventor
Fumiki Sone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP15838679A priority Critical patent/JPS5680705A/en
Publication of JPS5680705A publication Critical patent/JPS5680705A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the malfunction and falut of an external device by permitting a controller, performing program operation, to AND the output of a monostable multivibrator, triggered in every routine which passes through within constant time and a control output.
CONSTITUTION: On I/O board 4 of the controller, output interface circuit 41 generates trigger pulse eT in addition to normal control output signals eb and es. In normal operation, trigger pulse eT is generated every time the routine which passes through at least once within constant time T and applied to retrigger tupe monostable multivibrator (MMV)42 whose output pulse width is greater than T. Danger signal eD of the output interface circuit is ANDed with negative pulse Q' of MMV42 and safety-side signal eS is ORed with positive pulse Q to apply AND and OR signals to the external device, so that even if a microprocessor enters into a runaway state, the accident of the external device can be prevented.
COPYRIGHT: (C)1981,JPO&Japio
JP15838679A 1979-12-06 1979-12-06 Controller Pending JPS5680705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15838679A JPS5680705A (en) 1979-12-06 1979-12-06 Controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15838679A JPS5680705A (en) 1979-12-06 1979-12-06 Controller

Publications (1)

Publication Number Publication Date
JPS5680705A true JPS5680705A (en) 1981-07-02

Family

ID=15670581

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15838679A Pending JPS5680705A (en) 1979-12-06 1979-12-06 Controller

Country Status (1)

Country Link
JP (1) JPS5680705A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11685819B2 (en) 2018-12-07 2023-06-27 Sabic Global Technologies B.V. Polyolefin compositions with improved oxygen scavenging capability

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11685819B2 (en) 2018-12-07 2023-06-27 Sabic Global Technologies B.V. Polyolefin compositions with improved oxygen scavenging capability

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