JPS5679349A - Address assignment system to function processing device - Google Patents

Address assignment system to function processing device

Info

Publication number
JPS5679349A
JPS5679349A JP15557379A JP15557379A JPS5679349A JP S5679349 A JPS5679349 A JP S5679349A JP 15557379 A JP15557379 A JP 15557379A JP 15557379 A JP15557379 A JP 15557379A JP S5679349 A JPS5679349 A JP S5679349A
Authority
JP
Japan
Prior art keywords
function processing
processing device
result
assigned
read out
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15557379A
Other languages
Japanese (ja)
Inventor
Yukinobu Ito
Nobutoshi Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15557379A priority Critical patent/JPS5679349A/en
Publication of JPS5679349A publication Critical patent/JPS5679349A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to read out the result of function processing at a high speed by a slight burden of CPU, by assigning plural memory addresses to the function processing device, designating the assigned memory address, and reading out one by one the result of function processing.
CONSTITUTION: When the memory address assigned to the function processing device 1 is designated by the DMA2, the data which have been set to the registers 3, 4 are added to the data of A+Δ by the adder 5, and the operation result is read out through the interface 6. When said reading-out has been finished, the addition result is set to the register 3. When the assigned address is designated and read out one by one, the operation result corresponding to the memory address is obtained one by one. In this way, the result of function processing of plural memory addresses assigned to the function processing device can be read out at a high speed by a small burden of CPU.
COPYRIGHT: (C)1981,JPO&Japio
JP15557379A 1979-12-03 1979-12-03 Address assignment system to function processing device Pending JPS5679349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15557379A JPS5679349A (en) 1979-12-03 1979-12-03 Address assignment system to function processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15557379A JPS5679349A (en) 1979-12-03 1979-12-03 Address assignment system to function processing device

Publications (1)

Publication Number Publication Date
JPS5679349A true JPS5679349A (en) 1981-06-29

Family

ID=15608992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15557379A Pending JPS5679349A (en) 1979-12-03 1979-12-03 Address assignment system to function processing device

Country Status (1)

Country Link
JP (1) JPS5679349A (en)

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