JPS5679344A - Parity counting circuit - Google Patents

Parity counting circuit

Info

Publication number
JPS5679344A
JPS5679344A JP15418679A JP15418679A JPS5679344A JP S5679344 A JPS5679344 A JP S5679344A JP 15418679 A JP15418679 A JP 15418679A JP 15418679 A JP15418679 A JP 15418679A JP S5679344 A JPS5679344 A JP S5679344A
Authority
JP
Japan
Prior art keywords
circuit
initializing
parity
pulse
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15418679A
Other languages
Japanese (ja)
Other versions
JPS593783B2 (en
Inventor
Takayuki Ogura
Yuzo Fujii
Kenzo Nakabashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54154186A priority Critical patent/JPS593783B2/en
Publication of JPS5679344A publication Critical patent/JPS5679344A/en
Publication of JPS593783B2 publication Critical patent/JPS593783B2/en
Expired legal-status Critical Current

Links

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  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE: To make it possible not to require a special time for initializing, even in case of operation by the speed which is nearly the threshold speed of the FF circuit, by initializing the FF circuit by the data value itself.
CONSTITUTION: When a series data which is input to the terminal 11 is "1", a clock which is input to the terminal 12 is inverted by the FF circuit 16, and the operation for counting the parity is executed. The circuit 16 is initialized by making a preset pulse and a clear pulse output, when the value of the head data of the parity counting section is "1", and when the value of the head data is "0", respectively. In this regard, in case of initializing, when an initializing pulse is applied from the terminal 17, the clock pulse is not sent to the circuit 16 but becomes a toothless state, and the circuit 16 does not execute the clock operation. In this way, since a time of 1 bit portion is taken for preset or clear, it is unnecessary to use a special high speed operation element for only the parity circuit.
COPYRIGHT: (C)1981,JPO&Japio
JP54154186A 1979-11-30 1979-11-30 parity counting circuit Expired JPS593783B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54154186A JPS593783B2 (en) 1979-11-30 1979-11-30 parity counting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54154186A JPS593783B2 (en) 1979-11-30 1979-11-30 parity counting circuit

Publications (2)

Publication Number Publication Date
JPS5679344A true JPS5679344A (en) 1981-06-29
JPS593783B2 JPS593783B2 (en) 1984-01-26

Family

ID=15578710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54154186A Expired JPS593783B2 (en) 1979-11-30 1979-11-30 parity counting circuit

Country Status (1)

Country Link
JP (1) JPS593783B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01121721U (en) * 1987-12-24 1989-08-17

Also Published As

Publication number Publication date
JPS593783B2 (en) 1984-01-26

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