JPS5676850A - Microcomputer - Google Patents

Microcomputer

Info

Publication number
JPS5676850A
JPS5676850A JP15318079A JP15318079A JPS5676850A JP S5676850 A JPS5676850 A JP S5676850A JP 15318079 A JP15318079 A JP 15318079A JP 15318079 A JP15318079 A JP 15318079A JP S5676850 A JPS5676850 A JP S5676850A
Authority
JP
Japan
Prior art keywords
latch
halt
output
microcomputer
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15318079A
Other languages
Japanese (ja)
Inventor
Masahiro Mikami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP15318079A priority Critical patent/JPS5676850A/en
Publication of JPS5676850A publication Critical patent/JPS5676850A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To ensure an easy continuation of the program execution following the halt command, by starting the operation of a microcomputer after setting the input terminal at "0" and resetting the halt latch.
CONSTITUTION: The halt latch 7 is reset by the pulse supplied to the terminal 1 and when the power supply is made, and then set by the command decoder circuit 17 with supply of the halt command when the stop input terminal 4 is at the "0" level. When the output of the latch 7 is supplied to the circuit 17, the output is put under the halt state to discontinue the program execution of the microcomputer. Then the terminal 4 is set at "1", and thus the latch 7 is reset. But the output 12 of the gate 11 is kept at "1" with no execution given to the program. Then the terminal 4 is set at "0", and thus the latch 7 is reset with the output 12 set at the 0 level. Thus the execution is started for the microcomputer. As a result, the program execution can be continued easily following the next halt command.
COPYRIGHT: (C)1981,JPO&Japio
JP15318079A 1979-11-27 1979-11-27 Microcomputer Pending JPS5676850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15318079A JPS5676850A (en) 1979-11-27 1979-11-27 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15318079A JPS5676850A (en) 1979-11-27 1979-11-27 Microcomputer

Publications (1)

Publication Number Publication Date
JPS5676850A true JPS5676850A (en) 1981-06-24

Family

ID=15556789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15318079A Pending JPS5676850A (en) 1979-11-27 1979-11-27 Microcomputer

Country Status (1)

Country Link
JP (1) JPS5676850A (en)

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