JPS5676057A - Peak detection system - Google Patents

Peak detection system

Info

Publication number
JPS5676057A
JPS5676057A JP15295579A JP15295579A JPS5676057A JP S5676057 A JPS5676057 A JP S5676057A JP 15295579 A JP15295579 A JP 15295579A JP 15295579 A JP15295579 A JP 15295579A JP S5676057 A JPS5676057 A JP S5676057A
Authority
JP
Japan
Prior art keywords
signal
differentiated
order
point
intersection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15295579A
Other languages
Japanese (ja)
Other versions
JPH0235947B2 (en
Inventor
Kazuo Isaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15295579A priority Critical patent/JPH0235947B2/en
Publication of JPS5676057A publication Critical patent/JPS5676057A/en
Publication of JPH0235947B2 publication Critical patent/JPH0235947B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE: To eliminate an erronous detection of an inflection point other than a correct peak point by a method wherein a zero point of intersection of a differentiated signal of 1st order during a period of time when an amplitude of a differentiated signal of 2nd order of an analog signal exceeds the griven value for a given period of time or more is detected as a peak point.
CONSTITUTION: An input analog signal 1 enters a differentiator 2 and the signal is 1st order differentiated thereat, the differentiated output enters a comparator 7 and a zero point of intersection is detected. And together with this it enters a differentiator 3 and the signal is 2nd order differentiated thereat. The 2nd under differential signal is sliced on a given level through a unit 4 and thereafter, it is made into a pulse having a constant time width and supplied to a logical circuit 9. And when the 2nd order differential signal continues to retain an amplitude exceeding a slice level for given period of time or more, the circuit 9 detects a zero point of intersection detection signal delayed through a delay circuit 8 as a peak point of the input analog signal.
COPYRIGHT: (C)1981,JPO&Japio
JP15295579A 1979-11-28 1979-11-28 PIIKUKENSHUTSUSOCHI Expired - Lifetime JPH0235947B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15295579A JPH0235947B2 (en) 1979-11-28 1979-11-28 PIIKUKENSHUTSUSOCHI

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15295579A JPH0235947B2 (en) 1979-11-28 1979-11-28 PIIKUKENSHUTSUSOCHI

Publications (2)

Publication Number Publication Date
JPS5676057A true JPS5676057A (en) 1981-06-23
JPH0235947B2 JPH0235947B2 (en) 1990-08-14

Family

ID=15551807

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15295579A Expired - Lifetime JPH0235947B2 (en) 1979-11-28 1979-11-28 PIIKUKENSHUTSUSOCHI

Country Status (1)

Country Link
JP (1) JPH0235947B2 (en)

Also Published As

Publication number Publication date
JPH0235947B2 (en) 1990-08-14

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