JPS56734A - Delay equalization circuit network - Google Patents

Delay equalization circuit network

Info

Publication number
JPS56734A
JPS56734A JP7654079A JP7654079A JPS56734A JP S56734 A JPS56734 A JP S56734A JP 7654079 A JP7654079 A JP 7654079A JP 7654079 A JP7654079 A JP 7654079A JP S56734 A JPS56734 A JP S56734A
Authority
JP
Japan
Prior art keywords
circuit
transfer function
equation
fed
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7654079A
Other languages
Japanese (ja)
Inventor
Hiroshi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7654079A priority Critical patent/JPS56734A/en
Publication of JPS56734A publication Critical patent/JPS56734A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/14—Control of transmission; Equalising characterised by the equalising network used
    • H04B3/146—Control of transmission; Equalising characterised by the equalising network used using phase-frequency equalisers
    • H04B3/147—Control of transmission; Equalising characterised by the equalising network used using phase-frequency equalisers fixed equalisers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:To reduce the number of coils and to reduce the inductance of coil, by providing the first circuit of which transfer function is [+ or -2U(P)]/G(P)+U(P)] [where; G(P) and U(P) are respectively an even and an odd function]. CONSTITUTION:The signal at the input terminal 11 of the delay equalization circuit network is respectively fed to the circuit 12 of which transfer function is 1 and the circuit 13 of which transfer function is [-2U(P)]/[G(P)+U(P)] (where; G(P) and U(P) are respectively an even and an odd function], and the output of the circuits 12, 13 is added at the addition circuit 14 to be fed to the output terminal 15. In realizing the transfer function T(P) expressed in equation (3), equation (3) is transformed into as equation (4), and the circuit realizing equation (4) is as shown in Figure. Further, the circuit network to realize the transfer function of the second term of equation (4) is the circuit within dotted lines of the circuit 13, and the input signal is divided with the parallel circuit of resistance 16, capacitor 17 and coil 18 and fed to the inverting input side of the operational amplifier 21 via the resistor 19, and the output is negative-fed-back via the resistor 22. Taking the transfer function of the circuit 13 as [2U(P)]/[G(P)+U(P)], the circuit 14 shows a subtraction circuit.
JP7654079A 1979-06-18 1979-06-18 Delay equalization circuit network Pending JPS56734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7654079A JPS56734A (en) 1979-06-18 1979-06-18 Delay equalization circuit network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7654079A JPS56734A (en) 1979-06-18 1979-06-18 Delay equalization circuit network

Publications (1)

Publication Number Publication Date
JPS56734A true JPS56734A (en) 1981-01-07

Family

ID=13608094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7654079A Pending JPS56734A (en) 1979-06-18 1979-06-18 Delay equalization circuit network

Country Status (1)

Country Link
JP (1) JPS56734A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11439364B2 (en) 2013-03-15 2022-09-13 Bfly Operations, Inc. Ultrasonic imaging devices, systems and methods

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11439364B2 (en) 2013-03-15 2022-09-13 Bfly Operations, Inc. Ultrasonic imaging devices, systems and methods

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