JPS567331B2 - - Google Patents
Info
- Publication number
- JPS567331B2 JPS567331B2 JP10913877A JP10913877A JPS567331B2 JP S567331 B2 JPS567331 B2 JP S567331B2 JP 10913877 A JP10913877 A JP 10913877A JP 10913877 A JP10913877 A JP 10913877A JP S567331 B2 JPS567331 B2 JP S567331B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
- H03K19/09429—Multistate logic one of the states being the high impedance or floating state
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10913877A JPS5442948A (en) | 1977-09-10 | 1977-09-10 | Ternary converter circuit |
| US05/941,256 US4217502A (en) | 1977-09-10 | 1978-09-11 | Converter producing three output states |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10913877A JPS5442948A (en) | 1977-09-10 | 1977-09-10 | Ternary converter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5442948A JPS5442948A (en) | 1979-04-05 |
| JPS567331B2 true JPS567331B2 (en, 2012) | 1981-02-17 |
Family
ID=14502549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10913877A Granted JPS5442948A (en) | 1977-09-10 | 1977-09-10 | Ternary converter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5442948A (en, 2012) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55166312A (en) * | 1979-06-13 | 1980-12-25 | Nec Corp | Linear voltage-current converter |
| JPS57203334A (en) * | 1981-06-08 | 1982-12-13 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPH04117029A (ja) * | 1990-08-31 | 1992-04-17 | Nec Ic Microcomput Syst Ltd | レベルダウン回路 |
-
1977
- 1977-09-10 JP JP10913877A patent/JPS5442948A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5442948A (en) | 1979-04-05 |