JPS5671890A - Signal recording device - Google Patents

Signal recording device

Info

Publication number
JPS5671890A
JPS5671890A JP14904579A JP14904579A JPS5671890A JP S5671890 A JPS5671890 A JP S5671890A JP 14904579 A JP14904579 A JP 14904579A JP 14904579 A JP14904579 A JP 14904579A JP S5671890 A JPS5671890 A JP S5671890A
Authority
JP
Japan
Prior art keywords
signal
period
change
control
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14904579A
Other languages
Japanese (ja)
Inventor
Tsutomu Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14904579A priority Critical patent/JPS5671890A/en
Publication of JPS5671890A publication Critical patent/JPS5671890A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To increase the efficiency of memory usage, by recording the signal part rapid in the change in details, through the change of sampling period of input signal according to the rate of change.
CONSTITUTION: When a signal 2a proportional to the input signal 1a is in excess of the signal Vf made of the reference voltage corresponding to the A/D conversion start voltage at the input of the comparator 4, the comparator 4 makes the signal 4a as "1" and inputs it to the control circuit 9 to start the converting operation through the supply of the signal 9a to the A/D converter 3. The signal 9a is the signal to control the converting start period of the converter 3, that is, the signal to control the converting speed, and consists of the differentiation signal 8a and a pulse having the period changed according to the signal 10a specifying the sampling speed. The signal 3a digitized with the period like this is in accordance with the signal 9b operated as the write-in control signal in which the period is changed in synchronizing with the signal 9a and written in the memory 5 as the data. Accordingly, the signal part rapid in the change is recorded in details and the usage efficiency of memory can be increased.
COPYRIGHT: (C)1981,JPO&Japio
JP14904579A 1979-11-14 1979-11-14 Signal recording device Pending JPS5671890A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14904579A JPS5671890A (en) 1979-11-14 1979-11-14 Signal recording device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14904579A JPS5671890A (en) 1979-11-14 1979-11-14 Signal recording device

Publications (1)

Publication Number Publication Date
JPS5671890A true JPS5671890A (en) 1981-06-15

Family

ID=15466437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14904579A Pending JPS5671890A (en) 1979-11-14 1979-11-14 Signal recording device

Country Status (1)

Country Link
JP (1) JPS5671890A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5885997A (en) * 1981-11-18 1983-05-23 Neptune:Kk Analog signal reproducer
JPH04137821A (en) * 1990-09-27 1992-05-12 Sharp Corp A/d converter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5885997A (en) * 1981-11-18 1983-05-23 Neptune:Kk Analog signal reproducer
JPS6146920B2 (en) * 1981-11-18 1986-10-16 Nepuchuun Kk
JPH04137821A (en) * 1990-09-27 1992-05-12 Sharp Corp A/d converter

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