JPS5669933A - Pulse frequency dividing circuit - Google Patents

Pulse frequency dividing circuit

Info

Publication number
JPS5669933A
JPS5669933A JP14561479A JP14561479A JPS5669933A JP S5669933 A JPS5669933 A JP S5669933A JP 14561479 A JP14561479 A JP 14561479A JP 14561479 A JP14561479 A JP 14561479A JP S5669933 A JPS5669933 A JP S5669933A
Authority
JP
Japan
Prior art keywords
frequency
circuit
dividing circuit
frequency dividing
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14561479A
Other languages
Japanese (ja)
Inventor
Shinichi Shimomura
Kazuo Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14561479A priority Critical patent/JPS5669933A/en
Publication of JPS5669933A publication Critical patent/JPS5669933A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/08—Output circuits

Landscapes

  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)

Abstract

PURPOSE:To obtain frequency-divided pulses of a constant duty ratio without a phase shift by providing a gate circuit that resets the 2nd frequency dividing circuit by the output of the 1st frequency dividing circuit and FF that using outputs of the 1st and 2nd frequency dividing circuit as clock and clear signals. CONSTITUTION:Frequency dividing circuit 1 frequency-divides an input pulse signal at integer frequency-division rate 1/N and frequency dividing circuit 2 frequency-divides the same input pulse at integer frequency-division ratio 1/M. Then, the gate circuit that resets circuit 2 by the output of circuit 1 and D type FF4 that uses the output of circuit 1 as a clock signal and that of circuit 2 as a clear signal are both provided. Consequently, frequency-divided pulses of a constant duty ratio without a phase shift can be obtained.
JP14561479A 1979-11-10 1979-11-10 Pulse frequency dividing circuit Pending JPS5669933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14561479A JPS5669933A (en) 1979-11-10 1979-11-10 Pulse frequency dividing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14561479A JPS5669933A (en) 1979-11-10 1979-11-10 Pulse frequency dividing circuit

Publications (1)

Publication Number Publication Date
JPS5669933A true JPS5669933A (en) 1981-06-11

Family

ID=15389099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14561479A Pending JPS5669933A (en) 1979-11-10 1979-11-10 Pulse frequency dividing circuit

Country Status (1)

Country Link
JP (1) JPS5669933A (en)

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