JPS5668034A - Initializing circuit for counter circuit - Google Patents

Initializing circuit for counter circuit

Info

Publication number
JPS5668034A
JPS5668034A JP14433079A JP14433079A JPS5668034A JP S5668034 A JPS5668034 A JP S5668034A JP 14433079 A JP14433079 A JP 14433079A JP 14433079 A JP14433079 A JP 14433079A JP S5668034 A JPS5668034 A JP S5668034A
Authority
JP
Japan
Prior art keywords
reset
gate
circuit
signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14433079A
Other languages
Japanese (ja)
Other versions
JPS6349934B2 (en
Inventor
Masashi Mizunoe
Yukihiko Ido
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14433079A priority Critical patent/JPS5668034A/en
Publication of JPS5668034A publication Critical patent/JPS5668034A/en
Publication of JPS6349934B2 publication Critical patent/JPS6349934B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/38—Starting, stopping or resetting the counter

Landscapes

  • Electronic Switches (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To initialize a counter circuit securely by supplying a reset signal to a counter stage and then by releasing the reset signal by detecting the most significant digit bit is being reset. CONSTITUTION:When a reset pulse is inputted to input terminal S, NAND gate 20 outputs a signal that falls at the rise of the reset pulse and NAND gate 21 outputs a signal that falls at the fall of the reset pulse. Then, the output of gate 21 resets series-connected FFs of the counter circuit successively to apply the reset output signal for the most significant digit bit to reset input terminal RS of gate 20. The output of gate 20 rises, and consequently the output of gate 21 also rises. Initializing circuit B like this is constituted by using a buffer and latch circuit and never reduces the pulse width. Therefore, the clearing operation of the counter circuit is secured.
JP14433079A 1979-11-09 1979-11-09 Initializing circuit for counter circuit Granted JPS5668034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14433079A JPS5668034A (en) 1979-11-09 1979-11-09 Initializing circuit for counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14433079A JPS5668034A (en) 1979-11-09 1979-11-09 Initializing circuit for counter circuit

Publications (2)

Publication Number Publication Date
JPS5668034A true JPS5668034A (en) 1981-06-08
JPS6349934B2 JPS6349934B2 (en) 1988-10-06

Family

ID=15359593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14433079A Granted JPS5668034A (en) 1979-11-09 1979-11-09 Initializing circuit for counter circuit

Country Status (1)

Country Link
JP (1) JPS5668034A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5399864A (en) * 1977-02-12 1978-08-31 Nec Corp Counter circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5399864A (en) * 1977-02-12 1978-08-31 Nec Corp Counter circuit

Also Published As

Publication number Publication date
JPS6349934B2 (en) 1988-10-06

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