JPS5664580A - Synchronizing circuit for record signal display unit - Google Patents

Synchronizing circuit for record signal display unit

Info

Publication number
JPS5664580A
JPS5664580A JP13991579A JP13991579A JPS5664580A JP S5664580 A JPS5664580 A JP S5664580A JP 13991579 A JP13991579 A JP 13991579A JP 13991579 A JP13991579 A JP 13991579A JP S5664580 A JPS5664580 A JP S5664580A
Authority
JP
Japan
Prior art keywords
circuit
signal
clock signal
horizontal synchronous
central arithmetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13991579A
Other languages
Japanese (ja)
Inventor
Kiyoshi Hiramatsu
Masutomi Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13991579A priority Critical patent/JPS5664580A/en
Publication of JPS5664580A publication Critical patent/JPS5664580A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Television Systems (AREA)

Abstract

PURPOSE:To secure the matching of the display timing during the process of the cycle steal, by detecting the clock signal for driving of the central arithmetic process circuit which is produced in the begining of the horizontal scanning and then extending the pulse duration of the clock signal up to a certain time point from the horizontal synchronous signal. CONSTITUTION:The synchronous delaying circuit 9 using the horizontal synchronous signal for the input delivers the signals A and C to the fundamental clock generating circuit 10 and the generating circuit 11 of the detection pulse signal B respectively. The signal B is compared with the clock signal H of the central arithmetic process circuit at the detection circuit 13, and a high level is supplied to the detection holding circuit 14. The dividing circuit 15 is made inactive during the high level, and the section is extended for the section of the clock signal G of the central arithmetic process circuit. The reset of the circuit 14 is delayed by a fixed time from the horizontal synchronous signal, and thus the resetting is carried out in synchronization with the horizontal synchronous signal to secure a synchronization with the signal H. Thus no inconvenience is caused to the cycle steal process.
JP13991579A 1979-10-31 1979-10-31 Synchronizing circuit for record signal display unit Pending JPS5664580A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13991579A JPS5664580A (en) 1979-10-31 1979-10-31 Synchronizing circuit for record signal display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13991579A JPS5664580A (en) 1979-10-31 1979-10-31 Synchronizing circuit for record signal display unit

Publications (1)

Publication Number Publication Date
JPS5664580A true JPS5664580A (en) 1981-06-01

Family

ID=15256602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13991579A Pending JPS5664580A (en) 1979-10-31 1979-10-31 Synchronizing circuit for record signal display unit

Country Status (1)

Country Link
JP (1) JPS5664580A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06208351A (en) * 1992-10-30 1994-07-26 Internatl Business Mach Corp <Ibm> Multimedia display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06208351A (en) * 1992-10-30 1994-07-26 Internatl Business Mach Corp <Ibm> Multimedia display device

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