JPS5660092A - Method of treating penetrating wall for bothhside printed circuit board - Google Patents

Method of treating penetrating wall for bothhside printed circuit board

Info

Publication number
JPS5660092A
JPS5660092A JP13563879A JP13563879A JPS5660092A JP S5660092 A JPS5660092 A JP S5660092A JP 13563879 A JP13563879 A JP 13563879A JP 13563879 A JP13563879 A JP 13563879A JP S5660092 A JPS5660092 A JP S5660092A
Authority
JP
Japan
Prior art keywords
bothhside
circuit board
printed circuit
penetrating wall
treating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13563879A
Other languages
Japanese (ja)
Inventor
Eiichi Tsunashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13563879A priority Critical patent/JPS5660092A/en
Publication of JPS5660092A publication Critical patent/JPS5660092A/en
Pending legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP13563879A 1979-10-19 1979-10-19 Method of treating penetrating wall for bothhside printed circuit board Pending JPS5660092A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13563879A JPS5660092A (en) 1979-10-19 1979-10-19 Method of treating penetrating wall for bothhside printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13563879A JPS5660092A (en) 1979-10-19 1979-10-19 Method of treating penetrating wall for bothhside printed circuit board

Publications (1)

Publication Number Publication Date
JPS5660092A true JPS5660092A (en) 1981-05-23

Family

ID=15156481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13563879A Pending JPS5660092A (en) 1979-10-19 1979-10-19 Method of treating penetrating wall for bothhside printed circuit board

Country Status (1)

Country Link
JP (1) JPS5660092A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817269B2 (en) * 1988-05-11 1996-02-21 株式会社ソフィアシステムズ Circuit lighter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS534851A (en) * 1976-07-02 1978-01-17 Sharp Kk Through hole printed substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS534851A (en) * 1976-07-02 1978-01-17 Sharp Kk Through hole printed substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817269B2 (en) * 1988-05-11 1996-02-21 株式会社ソフィアシステムズ Circuit lighter

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