JPS5658119A - Reader for video format signal including pulse train information signal - Google Patents

Reader for video format signal including pulse train information signal

Info

Publication number
JPS5658119A
JPS5658119A JP13463079A JP13463079A JPS5658119A JP S5658119 A JPS5658119 A JP S5658119A JP 13463079 A JP13463079 A JP 13463079A JP 13463079 A JP13463079 A JP 13463079A JP S5658119 A JPS5658119 A JP S5658119A
Authority
JP
Japan
Prior art keywords
level
fixed
fixed level
signal
pedestal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13463079A
Other languages
Japanese (ja)
Inventor
Yoshiaki Moriyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP13463079A priority Critical patent/JPS5658119A/en
Publication of JPS5658119A publication Critical patent/JPS5658119A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Digital Magnetic Recording (AREA)

Abstract

PURPOSE: To reduce the data reading error rate, by clamping the pedestal level of the video format signal at a fixed level and at the same time controlling the peak level of the pulse train signal nearly at a fixed level to use it for the comparison input of the comparison output stage.
CONSTITUTION: The pedestal level of the pedestal clamping circuit 2 is fixed at the fixed level VPD, and at the same time the output VC according to the difference between the data peak and the fixed level is generated at the differential amplifier 4. Thus the amplitude of the pulse signal is controlled at a fixed level by the voltage control amplifier VCA1, and accordingly the data peak VPK is set at a fixed level. As a result, both the levels VPD and VPK become constant, and thus the optimum reading is possible for the PCM data regardless of the waveform of the input signal by setting previously the comparison level VTH of the comparator 5 at a desired level.
COPYRIGHT: (C)1981,JPO&Japio
JP13463079A 1979-10-18 1979-10-18 Reader for video format signal including pulse train information signal Pending JPS5658119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13463079A JPS5658119A (en) 1979-10-18 1979-10-18 Reader for video format signal including pulse train information signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13463079A JPS5658119A (en) 1979-10-18 1979-10-18 Reader for video format signal including pulse train information signal

Publications (1)

Publication Number Publication Date
JPS5658119A true JPS5658119A (en) 1981-05-21

Family

ID=15132857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13463079A Pending JPS5658119A (en) 1979-10-18 1979-10-18 Reader for video format signal including pulse train information signal

Country Status (1)

Country Link
JP (1) JPS5658119A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5483816A (en) * 1977-12-16 1979-07-04 Victor Co Of Japan Ltd Digital signal generator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5483816A (en) * 1977-12-16 1979-07-04 Victor Co Of Japan Ltd Digital signal generator

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