JPS5532212A - Tape recorder - Google Patents

Tape recorder

Info

Publication number
JPS5532212A
JPS5532212A JP10298978A JP10298978A JPS5532212A JP S5532212 A JPS5532212 A JP S5532212A JP 10298978 A JP10298978 A JP 10298978A JP 10298978 A JP10298978 A JP 10298978A JP S5532212 A JPS5532212 A JP S5532212A
Authority
JP
Japan
Prior art keywords
circuit
gate
output
commute
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10298978A
Other languages
Japanese (ja)
Inventor
Tsutomu Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP10298978A priority Critical patent/JPS5532212A/en
Publication of JPS5532212A publication Critical patent/JPS5532212A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to select desired group signals automatically and rapidly by recording a discrimination address signal on an unrecorded track while forming the unrecorded track between group signals through re-commute operation.
CONSTITUTION: The output terminal of re-commute switch S1 is connected to 1st timer circuit 1 with fixed re-commute time and 2nd timer circuit 2 with shorter time than the above-mentioned re-commute time, and the output of the 1st circuit 1 is supplied to control circuit 4 controlling driver circuit 3 and AND gate 5. The output of the 2nd circuit 2 is supplied to the other input terminal of AND gate 5 via inverter 6. Signals from address signal generating circuit 7 are supplied to gate circuit 8, which is open when AND gate 5 generates its output to allow an address signal to pass through, and it is recorded on tape 12 via recording amplifier 10. Therefore, assigning an address makes it possible to select desired group signals automatically and rapidly.
COPYRIGHT: (C)1980,JPO&Japio
JP10298978A 1978-08-24 1978-08-24 Tape recorder Pending JPS5532212A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10298978A JPS5532212A (en) 1978-08-24 1978-08-24 Tape recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10298978A JPS5532212A (en) 1978-08-24 1978-08-24 Tape recorder

Publications (1)

Publication Number Publication Date
JPS5532212A true JPS5532212A (en) 1980-03-06

Family

ID=14342103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10298978A Pending JPS5532212A (en) 1978-08-24 1978-08-24 Tape recorder

Country Status (1)

Country Link
JP (1) JPS5532212A (en)

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