JPS5656056A - Automatic frequency control circuit - Google Patents
Automatic frequency control circuitInfo
- Publication number
- JPS5656056A JPS5656056A JP13150379A JP13150379A JPS5656056A JP S5656056 A JPS5656056 A JP S5656056A JP 13150379 A JP13150379 A JP 13150379A JP 13150379 A JP13150379 A JP 13150379A JP S5656056 A JPS5656056 A JP S5656056A
- Authority
- JP
- Japan
- Prior art keywords
- oscillator
- signal
- frequency
- oscillation frequency
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
PURPOSE:To perform waiting communication effectively by measuring and storing a voltage control oscillation frequency in a normal period, by measuing and storing an oscillation frequency fluctuating from the time of the stop of an input signal and then by controlling an oscillator with a signal voltage that corresponds to the difference between both frequencies. CONSTITUTION:The oscillation frequency of voltage control oscillator 2 used as a local oscillator is measured by counter 5. Its output is changed over by switching circuit SW2 according to the existence of input signal VS and led to memory 6 or 7. Each output is subtracted 8 and the frequency of oscillator 2 is controlled with the obtained difference signal. Consequently, when signal VS is intermitted, the frequency of oscillator 2 is controlled by this loop circuit, so that the waiting communication can be performed effectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13150379A JPS5656056A (en) | 1979-10-11 | 1979-10-11 | Automatic frequency control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13150379A JPS5656056A (en) | 1979-10-11 | 1979-10-11 | Automatic frequency control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5656056A true JPS5656056A (en) | 1981-05-16 |
JPS6213846B2 JPS6213846B2 (en) | 1987-03-30 |
Family
ID=15059534
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13150379A Granted JPS5656056A (en) | 1979-10-11 | 1979-10-11 | Automatic frequency control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5656056A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63158859U (en) * | 1987-04-03 | 1988-10-18 |
-
1979
- 1979-10-11 JP JP13150379A patent/JPS5656056A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6213846B2 (en) | 1987-03-30 |
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