JPS5650449A - Microprogram control unit - Google Patents

Microprogram control unit

Info

Publication number
JPS5650449A
JPS5650449A JP12761079A JP12761079A JPS5650449A JP S5650449 A JPS5650449 A JP S5650449A JP 12761079 A JP12761079 A JP 12761079A JP 12761079 A JP12761079 A JP 12761079A JP S5650449 A JPS5650449 A JP S5650449A
Authority
JP
Japan
Prior art keywords
circuit
signal
state
clock
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12761079A
Other languages
Japanese (ja)
Inventor
Harunobu Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12761079A priority Critical patent/JPS5650449A/en
Publication of JPS5650449A publication Critical patent/JPS5650449A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To reduce the hardware quantity and the number of steps and to shorten the state detection time through performing firmware, by stopping the clock signal until one of plural states is detected by state supervisory instructions.
CONSTITUTION: Clock signal generating circuit b' is controlled by clock stop indication signal 5 supplied from microprogram control circuit (a). Indication signal 5 has the function to stop clock signal 1 from circuit b' and is controlled by firmware. Further, clock restart indication signal 8 is generated from state detecting circuit (d) to make it possible to release stop of clock signal 7 supplied to control circuit (a). Circuit (d) receives interface signal 2 from circuit (a) when microprogram address 9 requires the state of hardware stored in microprogram interface circuit (c); and when circuit (d) detects a specific state, signal 8 is generated and supplied to circuit b' to generate signal 7 again.
COPYRIGHT: (C)1981,JPO&Japio
JP12761079A 1979-10-02 1979-10-02 Microprogram control unit Pending JPS5650449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12761079A JPS5650449A (en) 1979-10-02 1979-10-02 Microprogram control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12761079A JPS5650449A (en) 1979-10-02 1979-10-02 Microprogram control unit

Publications (1)

Publication Number Publication Date
JPS5650449A true JPS5650449A (en) 1981-05-07

Family

ID=14964335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12761079A Pending JPS5650449A (en) 1979-10-02 1979-10-02 Microprogram control unit

Country Status (1)

Country Link
JP (1) JPS5650449A (en)

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