JPS5647120A - Method and device for generating synchronizing signal of multiple system - Google Patents
Method and device for generating synchronizing signal of multiple systemInfo
- Publication number
- JPS5647120A JPS5647120A JP12444479A JP12444479A JPS5647120A JP S5647120 A JPS5647120 A JP S5647120A JP 12444479 A JP12444479 A JP 12444479A JP 12444479 A JP12444479 A JP 12444479A JP S5647120 A JPS5647120 A JP S5647120A
- Authority
- JP
- Japan
- Prior art keywords
- systems
- lagging
- leading
- signal
- synchronizing signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
PURPOSE:To attain accurate synchronous operation by checking synchronizing signals of other systems on the basis of that of the own system to detect whether a normal synchronizing signal leading or lagging and by correcting the own system. CONSTITUTION:Synchronizing signals TPb and TPc of other systems are inputted to synchronism deciding circuit 2. Synchronism deciding circuit 2 detects the rise and fall of synchronizing signals of other systems by using its-system leading signal FSP and its-system lagging signal LTP leading and lagging by constant phases, thereby deciding whether synchronizing signals of other systems are abnormal. When synchronizing signals of other systems are normally generated, the phase shift between the synchronizing signal of its system and those of other systems is further checked and information on leading and lagging is inputted to the majority-decision logic circuit to correct the synchronizing signal of its system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12444479A JPS5647120A (en) | 1979-09-27 | 1979-09-27 | Method and device for generating synchronizing signal of multiple system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12444479A JPS5647120A (en) | 1979-09-27 | 1979-09-27 | Method and device for generating synchronizing signal of multiple system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5647120A true JPS5647120A (en) | 1981-04-28 |
Family
ID=14885650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12444479A Pending JPS5647120A (en) | 1979-09-27 | 1979-09-27 | Method and device for generating synchronizing signal of multiple system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5647120A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6389041B1 (en) | 1997-12-05 | 2002-05-14 | Hitachi, Ltd. | Synchronization system and synchronization method of multisystem control apparatus |
-
1979
- 1979-09-27 JP JP12444479A patent/JPS5647120A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6389041B1 (en) | 1997-12-05 | 2002-05-14 | Hitachi, Ltd. | Synchronization system and synchronization method of multisystem control apparatus |
| US7158521B2 (en) | 1997-12-05 | 2007-01-02 | Hitachi, Ltd. | Synchronization system and synchronization method of multisystem control apparatus |
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