JPS5638655A - Microprocessor - Google Patents

Microprocessor

Info

Publication number
JPS5638655A
JPS5638655A JP11377879A JP11377879A JPS5638655A JP S5638655 A JPS5638655 A JP S5638655A JP 11377879 A JP11377879 A JP 11377879A JP 11377879 A JP11377879 A JP 11377879A JP S5638655 A JPS5638655 A JP S5638655A
Authority
JP
Japan
Prior art keywords
latch circuit
signal
circuit
microprocessor
time measuring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11377879A
Other languages
Japanese (ja)
Inventor
Toru Henmi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11377879A priority Critical patent/JPS5638655A/en
Publication of JPS5638655A publication Critical patent/JPS5638655A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain the timer signal at the output terminal, without the burden of software, by providing the time measuring circuit and the latch circuit of microprocessor in one chip.
CONSTITUTION: In the microprocessor, the time measuring circuit 1 constituted with the binary counter in 8-bit and generating the signal in the period of time set with the control section, latch circuit 2 taking the signal from the time measuring circuit 1 as sampling clock, and inversion circuit 6 invering the signal obtained at the output of latch circuit 2 and giving it to the input of the latch circuit 2, are provided in one chip. The output of the latch circuit 2 is connected to the external terminal 3. Since the timer signal is obtained at the terminal 3, buzzer can intermittently by energized through the connection of buzzer and lamp, enabling to flicker the lamp.
COPYRIGHT: (C)1981,JPO&Japio
JP11377879A 1979-09-05 1979-09-05 Microprocessor Pending JPS5638655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11377879A JPS5638655A (en) 1979-09-05 1979-09-05 Microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11377879A JPS5638655A (en) 1979-09-05 1979-09-05 Microprocessor

Publications (1)

Publication Number Publication Date
JPS5638655A true JPS5638655A (en) 1981-04-13

Family

ID=14620869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11377879A Pending JPS5638655A (en) 1979-09-05 1979-09-05 Microprocessor

Country Status (1)

Country Link
JP (1) JPS5638655A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804732B2 (en) 2002-03-29 2004-10-12 Denso Corporation Port sampling circuit apparatus incorporated in a microcomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804732B2 (en) 2002-03-29 2004-10-12 Denso Corporation Port sampling circuit apparatus incorporated in a microcomputer

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