JPS5636230A - Level converting circuit - Google Patents

Level converting circuit

Info

Publication number
JPS5636230A
JPS5636230A JP11177779A JP11177779A JPS5636230A JP S5636230 A JPS5636230 A JP S5636230A JP 11177779 A JP11177779 A JP 11177779A JP 11177779 A JP11177779 A JP 11177779A JP S5636230 A JPS5636230 A JP S5636230A
Authority
JP
Japan
Prior art keywords
turned
level
transistors
transistor
power source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11177779A
Other languages
Japanese (ja)
Other versions
JPH0225294B2 (en
Inventor
Koji Masuda
Masao Mizukami
Nobuaki Kitamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP11177779A priority Critical patent/JPS5636230A/en
Priority to US06/157,853 priority patent/US4356409A/en
Priority to DE19803024274 priority patent/DE3024274A1/en
Publication of JPS5636230A publication Critical patent/JPS5636230A/en
Publication of JPH0225294B2 publication Critical patent/JPH0225294B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01812—Interface arrangements with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To protect the output stage of a level converting circuit, by turning off the transistor, which makes the output high-level, by the output of the detecting circuit which detects fluctuation of the power source voltage. CONSTITUTION:When positive power source voltage VCC becomes large excessively or negative power source voltage VEE becomes small excessively, the bias voltage of node N3 becomes larger than 2VBE. Consequently, transistors Q5-Q7 are turned on, and transistor Q8 is turned on. Consequently, transistor Q20 is turned on, and the level of node N2 is made low-level, and transistors Q16 and Q17 are turned off, so that transistors Q17 and Q19 can be prevented from being turned on simultaneously.
JP11177779A 1979-06-29 1979-09-03 Level converting circuit Granted JPS5636230A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP11177779A JPS5636230A (en) 1979-09-03 1979-09-03 Level converting circuit
US06/157,853 US4356409A (en) 1979-06-29 1980-06-09 Level conversion circuit
DE19803024274 DE3024274A1 (en) 1979-06-29 1980-06-27 LEVEL CONVERTER CONTROL

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11177779A JPS5636230A (en) 1979-09-03 1979-09-03 Level converting circuit

Publications (2)

Publication Number Publication Date
JPS5636230A true JPS5636230A (en) 1981-04-09
JPH0225294B2 JPH0225294B2 (en) 1990-06-01

Family

ID=14569896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11177779A Granted JPS5636230A (en) 1979-06-29 1979-09-03 Level converting circuit

Country Status (1)

Country Link
JP (1) JPS5636230A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4998029A (en) * 1989-07-03 1991-03-05 Motorola, Inc. Dual supply ECL to TTL translator

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0680482U (en) * 1993-04-30 1994-11-15 東邦工業株式会社 Jigsaw puzzle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4998029A (en) * 1989-07-03 1991-03-05 Motorola, Inc. Dual supply ECL to TTL translator

Also Published As

Publication number Publication date
JPH0225294B2 (en) 1990-06-01

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