JPS5632894A - Channel test trunk circuit - Google Patents

Channel test trunk circuit

Info

Publication number
JPS5632894A
JPS5632894A JP10893179A JP10893179A JPS5632894A JP S5632894 A JPS5632894 A JP S5632894A JP 10893179 A JP10893179 A JP 10893179A JP 10893179 A JP10893179 A JP 10893179A JP S5632894 A JPS5632894 A JP S5632894A
Authority
JP
Japan
Prior art keywords
circuit
code
circuits
deciding
digital code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10893179A
Other languages
Japanese (ja)
Inventor
Hiroshi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10893179A priority Critical patent/JPS5632894A/en
Publication of JPS5632894A publication Critical patent/JPS5632894A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
    • H04M3/244—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for multiplex systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Interface Circuits In Exchanges (AREA)

Abstract

PURPOSE:To make the operation of a communication unit smooth by detecting all faults happening to a channel by deciding a coincidence and dissidence between a code-converted digital code on the channel and a digital code outputted from a code converting circuit. CONSTITUTION:The 1st and 2nd test pattern circuits 19 and 20 that outputs the 1st and 2nd test patterns, transmitting gates 9 and 10 that send the 1st and 2nd patterns to common lines 5 and 6, and inverters 22 and 23 are provided. Further, code converting circuit 21 that receives the outputs of circuits 19 and 20 and deciding circuit 16 that compares the output digital code of circuit 21 to a received digital code from common line 7 are provided. On the basis of a time slot signal to be tested from control circuit 13, test patterns are sent out of circuits 19 and 20 and deciding circuit 16 decides two digital codes generated by circuit 21, so that all faults happening to the channcel can be detected by the output from common line 7.
JP10893179A 1979-08-27 1979-08-27 Channel test trunk circuit Pending JPS5632894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10893179A JPS5632894A (en) 1979-08-27 1979-08-27 Channel test trunk circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10893179A JPS5632894A (en) 1979-08-27 1979-08-27 Channel test trunk circuit

Publications (1)

Publication Number Publication Date
JPS5632894A true JPS5632894A (en) 1981-04-02

Family

ID=14497278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10893179A Pending JPS5632894A (en) 1979-08-27 1979-08-27 Channel test trunk circuit

Country Status (1)

Country Link
JP (1) JPS5632894A (en)

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