JPS5629818A - Signal recording and reproducting device of pcm system - Google Patents

Signal recording and reproducting device of pcm system

Info

Publication number
JPS5629818A
JPS5629818A JP10383379A JP10383379A JPS5629818A JP S5629818 A JPS5629818 A JP S5629818A JP 10383379 A JP10383379 A JP 10383379A JP 10383379 A JP10383379 A JP 10383379A JP S5629818 A JPS5629818 A JP S5629818A
Authority
JP
Japan
Prior art keywords
circuit
control signal
clock
memory
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10383379A
Other languages
Japanese (ja)
Inventor
Koji Fukuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP10383379A priority Critical patent/JPS5629818A/en
Publication of JPS5629818A publication Critical patent/JPS5629818A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To enable to use the lower conversion frequency at modulation, and demodulation, by giving the specified phase relation to each clock supplied to the memory write-in control signal forming circuit and the memory readout control signal forming circuit.
CONSTITUTION: The digital signal obtained through the conversion of analog signal with the PCM system is inserted to the set section of the signal of specified format such as video signal format and recorded in VTR8, and the reproduced digital signal is converted into analog signal. In this recording system, the clock obtained through the frequency-division 62' of the output of the crystal oscillation circuit 61' is fed to the memory write-in control signal forming circuit 64. Further, the clock frequency-divided at the circuit 64 is given to the PLL circuit 66 as the control signal. The clock obtained through the frequency division 63' of the output of the circuit 66 is fed to the memory readout control signal forming circuit 65. As a result, the phase of clock to the circuits 64 and 65 has a given relation to obtain the balance between the write-in and readout of the memory 5.
COPYRIGHT: (C)1981,JPO&Japio
JP10383379A 1979-08-13 1979-08-13 Signal recording and reproducting device of pcm system Pending JPS5629818A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10383379A JPS5629818A (en) 1979-08-13 1979-08-13 Signal recording and reproducting device of pcm system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10383379A JPS5629818A (en) 1979-08-13 1979-08-13 Signal recording and reproducting device of pcm system

Publications (1)

Publication Number Publication Date
JPS5629818A true JPS5629818A (en) 1981-03-25

Family

ID=14364416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10383379A Pending JPS5629818A (en) 1979-08-13 1979-08-13 Signal recording and reproducting device of pcm system

Country Status (1)

Country Link
JP (1) JPS5629818A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9543099B2 (en) 2014-09-29 2017-01-10 Lsis Co., Ltd. Direct current relay

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9543099B2 (en) 2014-09-29 2017-01-10 Lsis Co., Ltd. Direct current relay

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