JPS5627426A - Studying equipment of stored program controller - Google Patents

Studying equipment of stored program controller

Info

Publication number
JPS5627426A
JPS5627426A JP10205679A JP10205679A JPS5627426A JP S5627426 A JPS5627426 A JP S5627426A JP 10205679 A JP10205679 A JP 10205679A JP 10205679 A JP10205679 A JP 10205679A JP S5627426 A JPS5627426 A JP S5627426A
Authority
JP
Japan
Prior art keywords
add
state
instruction
stored program
program controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10205679A
Other languages
Japanese (ja)
Other versions
JPS5826052B2 (en
Inventor
Shintaro Eguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54102056A priority Critical patent/JPS5826052B2/en
Publication of JPS5627426A publication Critical patent/JPS5627426A/en
Publication of JPS5826052B2 publication Critical patent/JPS5826052B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Electrically Operated Instructional Devices (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To make is possible to let a person in study know the operation of the constituent circuit of a stored program controller by visually displaying the operation state of the constituent circuit by the output of a provided signal generating circuit.
CONSTITUTION: Once decoder DEC decodes instruction code N, controller CTL sets part of a control signal and also displays the order of opening a gate. For example, when the instruction is Add, lamp LMP that corresponds to Add turns on and buttons for gate signals G1WG6 are manually operated in the order while the display of the register and main memory unit MM are confirmed. Consequently, the state of the progress of the operation of instruction Add is displayed on the binary or decimal scale, so that the progress state of the operation can clearly be understood.
COPYRIGHT: (C)1981,JPO&Japio
JP54102056A 1979-08-09 1979-08-09 Learning device for storage program control device Expired JPS5826052B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54102056A JPS5826052B2 (en) 1979-08-09 1979-08-09 Learning device for storage program control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54102056A JPS5826052B2 (en) 1979-08-09 1979-08-09 Learning device for storage program control device

Publications (2)

Publication Number Publication Date
JPS5627426A true JPS5627426A (en) 1981-03-17
JPS5826052B2 JPS5826052B2 (en) 1983-05-31

Family

ID=14317105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54102056A Expired JPS5826052B2 (en) 1979-08-09 1979-08-09 Learning device for storage program control device

Country Status (1)

Country Link
JP (1) JPS5826052B2 (en)

Also Published As

Publication number Publication date
JPS5826052B2 (en) 1983-05-31

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