JPS54139500A - Display circuit - Google Patents

Display circuit

Info

Publication number
JPS54139500A
JPS54139500A JP4803678A JP4803678A JPS54139500A JP S54139500 A JPS54139500 A JP S54139500A JP 4803678 A JP4803678 A JP 4803678A JP 4803678 A JP4803678 A JP 4803678A JP S54139500 A JPS54139500 A JP S54139500A
Authority
JP
Japan
Prior art keywords
circuit
luminance
position information
output
analog signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4803678A
Other languages
Japanese (ja)
Inventor
Hiroshi Morito
Kenji Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4803678A priority Critical patent/JPS54139500A/en
Publication of JPS54139500A publication Critical patent/JPS54139500A/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE: To obtain a matrix display unit which controls the luminance of each display element by combining the n-bit input signal showing the position information and the input analog signal to be displayed as the luminance.
CONSTITUTION: The n-bit input signal 1 showing the position information is decoded through decoder 2 and then delivered to driving circuit 3 in the form of the signal according to the position information. On the other hand, the analog signal according to the luminance to be displayed is applied to luminance control circuit 5 via input terminal 6. The output of circuit 2 is combined with the output of circuit 5 at circuit 3. And the display element selected by the output of circuit 2 among the display elements distributed to the matrix of p-line and q-row is lit up with the luminance in accordance with the analog signal.
COPYRIGHT: (C)1979,JPO&Japio
JP4803678A 1978-04-21 1978-04-21 Display circuit Pending JPS54139500A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4803678A JPS54139500A (en) 1978-04-21 1978-04-21 Display circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4803678A JPS54139500A (en) 1978-04-21 1978-04-21 Display circuit

Publications (1)

Publication Number Publication Date
JPS54139500A true JPS54139500A (en) 1979-10-29

Family

ID=12792076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4803678A Pending JPS54139500A (en) 1978-04-21 1978-04-21 Display circuit

Country Status (1)

Country Link
JP (1) JPS54139500A (en)

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