JPS551559A - Timer device - Google Patents

Timer device

Info

Publication number
JPS551559A
JPS551559A JP7465278A JP7465278A JPS551559A JP S551559 A JPS551559 A JP S551559A JP 7465278 A JP7465278 A JP 7465278A JP 7465278 A JP7465278 A JP 7465278A JP S551559 A JPS551559 A JP S551559A
Authority
JP
Japan
Prior art keywords
time
circuit
timer
display
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7465278A
Other languages
Japanese (ja)
Inventor
Mitsutoshi Yahagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP7465278A priority Critical patent/JPS551559A/en
Publication of JPS551559A publication Critical patent/JPS551559A/en
Pending legal-status Critical Current

Links

Landscapes

  • Measurement Of Predetermined Time Intervals (AREA)

Abstract

PURPOSE: To enable the set time of the timer to be simultaneously displayed together with the left time or elapsed time of the timer by providing a display body which analogically displays the time to the timer device.
CONSTITUTION: Time information is applied to decoder drivers 5 and 6 through a display selecting circuit 4 and is displayed in a digital display part 7 and analog display part 8. The display selecting circuit 4 is provided with five AND circuits 9 thru 13 and two OFF circuits 14, 15. The left time information from a substraction counter 16 is inputted to each one of the input ends of the AND circuits 10 and 11. The timer time information from a time memory circuit 17 is inputted to one input end of the AND circuit 13. A setting circuit 18 is capable of setting the time in a clock counter circuit 3 when switches S4, S5 are operated in a time display state and is capable of setting the memory in the time memory circuit 17 when the switches S4, S5 are operated in a time display state.
COPYRIGHT: (C)1980,JPO&Japio
JP7465278A 1978-06-20 1978-06-20 Timer device Pending JPS551559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7465278A JPS551559A (en) 1978-06-20 1978-06-20 Timer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7465278A JPS551559A (en) 1978-06-20 1978-06-20 Timer device

Publications (1)

Publication Number Publication Date
JPS551559A true JPS551559A (en) 1980-01-08

Family

ID=13553363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7465278A Pending JPS551559A (en) 1978-06-20 1978-06-20 Timer device

Country Status (1)

Country Link
JP (1) JPS551559A (en)

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