JPS5623007A - Amplifier for fine voltage - Google Patents

Amplifier for fine voltage

Info

Publication number
JPS5623007A
JPS5623007A JP9900079A JP9900079A JPS5623007A JP S5623007 A JPS5623007 A JP S5623007A JP 9900079 A JP9900079 A JP 9900079A JP 9900079 A JP9900079 A JP 9900079A JP S5623007 A JPS5623007 A JP S5623007A
Authority
JP
Japan
Prior art keywords
signal
sample
added
adder
sample hold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9900079A
Other languages
Japanese (ja)
Inventor
Kenji Odagiri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SPC Electronics Corp
Original Assignee
SPC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SPC Electronics Corp filed Critical SPC Electronics Corp
Priority to JP9900079A priority Critical patent/JPS5623007A/en
Publication of JPS5623007A publication Critical patent/JPS5623007A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/38—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To obtain the amplification factor of N times, by the N times' integration of fine input signal through the combination of adder with sample hold circuit. CONSTITUTION:Taking the signal at time(t) of the fine input signal e1 given to the input terminal 1 as e1(t), this signal e1(t) is fed to the adder 2 as added signal. Further, the added output signal from the 2nd sample hold circuit 5 is fed to the adder 2 as another added signal, allowing the addition with the fine input signal. The added output signal is the input signal to the 1st sample hold circuit 3, allowing sample hold to the sample command signal T1 from the control circuit 7. The addition output signal sample held is the input signal of the 2nd sample hold circuit 5, and it is sample-held with the sample command signal T2 from the control circuit T2 to be the added signal of the adder 2.
JP9900079A 1979-08-02 1979-08-02 Amplifier for fine voltage Pending JPS5623007A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9900079A JPS5623007A (en) 1979-08-02 1979-08-02 Amplifier for fine voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9900079A JPS5623007A (en) 1979-08-02 1979-08-02 Amplifier for fine voltage

Publications (1)

Publication Number Publication Date
JPS5623007A true JPS5623007A (en) 1981-03-04

Family

ID=14234694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9900079A Pending JPS5623007A (en) 1979-08-02 1979-08-02 Amplifier for fine voltage

Country Status (1)

Country Link
JP (1) JPS5623007A (en)

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