JPS5617545A - Timing phase control system for identification of high- speed duo-binary waveform - Google Patents

Timing phase control system for identification of high- speed duo-binary waveform

Info

Publication number
JPS5617545A
JPS5617545A JP9403979A JP9403979A JPS5617545A JP S5617545 A JPS5617545 A JP S5617545A JP 9403979 A JP9403979 A JP 9403979A JP 9403979 A JP9403979 A JP 9403979A JP S5617545 A JPS5617545 A JP S5617545A
Authority
JP
Japan
Prior art keywords
phase control
output
timing phase
timing
duo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9403979A
Other languages
Japanese (ja)
Inventor
Toshio Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9403979A priority Critical patent/JPS5617545A/en
Publication of JPS5617545A publication Critical patent/JPS5617545A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/497Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To prevent the out of leadin by setting forcedly the phase control voltage back into the lead in range in which the timing phase control is applied in case the phase control voltage reaches the upper or lower limit. CONSTITUTION:The transmitted digital signal is identified and reproduced by identifying/reproducing means 3 based on the timing signal of phase verying means 4. Then both the transmitted digital signal and the output of means 3 are applied to timing phase control signal generating means 5, and furthermore the output of means 15 and out-of-leadin detecting means 9. When means 9 detects that the timing phase control signal has reached the upper or lower limit, the output is delivered to reset pulse generating means 10. Receiving this output, reset pulse generating means 10 generates the periodical positive or negative polarity pulse train. This pulse train is set to a proper size through gain control means 14 and then applied to means 15. And means 4 is controlled by the output of means 15.
JP9403979A 1979-07-24 1979-07-24 Timing phase control system for identification of high- speed duo-binary waveform Pending JPS5617545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9403979A JPS5617545A (en) 1979-07-24 1979-07-24 Timing phase control system for identification of high- speed duo-binary waveform

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9403979A JPS5617545A (en) 1979-07-24 1979-07-24 Timing phase control system for identification of high- speed duo-binary waveform

Publications (1)

Publication Number Publication Date
JPS5617545A true JPS5617545A (en) 1981-02-19

Family

ID=14099418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9403979A Pending JPS5617545A (en) 1979-07-24 1979-07-24 Timing phase control system for identification of high- speed duo-binary waveform

Country Status (1)

Country Link
JP (1) JPS5617545A (en)

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