JPS56164679A - Synchronizing signal processing circuit - Google Patents
Synchronizing signal processing circuitInfo
- Publication number
- JPS56164679A JPS56164679A JP6743080A JP6743080A JPS56164679A JP S56164679 A JPS56164679 A JP S56164679A JP 6743080 A JP6743080 A JP 6743080A JP 6743080 A JP6743080 A JP 6743080A JP S56164679 A JPS56164679 A JP S56164679A
- Authority
- JP
- Japan
- Prior art keywords
- synchronizing signal
- circuit
- horizontal
- cut
- frequencies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
Abstract
PURPOSE:To reject unnecessary frequency components and to avoid the effect of noise, by connecting a low pass filter which cut-off the frequencies among 10- 20fh(horizontal scanning frequencies) between a video signal input terminal and a synchronizing separating circuit. CONSTITUTION:In a synchronizing signal processing circuit, between a video signal input terminal 1 and a synchronizing separation circuit 2, a low pass filter 7 which cut-off the frequencies between 10-20fh is connected. Thus, a horizontal synchronizing signal component only can pass through and the frequency component more than the cut-off frequency is rejected. Further, since only one polarity is picked up by adding or subtracting the output of the circuit 2 in the reversed polarity for the signal delaying 1/2 period of pulse width of the horizontal synchronizing signal, the horizontal synchronizing signal with the same pulse width as the equivalent pulse over the entire scanning period is obtained and the AFC sensitivity of the pulse width horizontal AFC circuit is made constant for the entire scanning period.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6743080A JPS56164679A (en) | 1980-05-21 | 1980-05-21 | Synchronizing signal processing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6743080A JPS56164679A (en) | 1980-05-21 | 1980-05-21 | Synchronizing signal processing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56164679A true JPS56164679A (en) | 1981-12-17 |
Family
ID=13344679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6743080A Pending JPS56164679A (en) | 1980-05-21 | 1980-05-21 | Synchronizing signal processing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56164679A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2644025A1 (en) * | 1989-03-03 | 1990-09-07 | Thomson Csf | Device for extracting "3 state" pulses in a noisy medium |
-
1980
- 1980-05-21 JP JP6743080A patent/JPS56164679A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2644025A1 (en) * | 1989-03-03 | 1990-09-07 | Thomson Csf | Device for extracting "3 state" pulses in a noisy medium |
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