JPS56164442A - Response system between microprogram processing devices - Google Patents

Response system between microprogram processing devices

Info

Publication number
JPS56164442A
JPS56164442A JP6803380A JP6803380A JPS56164442A JP S56164442 A JPS56164442 A JP S56164442A JP 6803380 A JP6803380 A JP 6803380A JP 6803380 A JP6803380 A JP 6803380A JP S56164442 A JPS56164442 A JP S56164442A
Authority
JP
Japan
Prior art keywords
signal
mpu3
auxiliary
information
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6803380A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6239790B2 (enrdf_load_stackoverflow
Inventor
Kazuhisa Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6803380A priority Critical patent/JPS56164442A/ja
Publication of JPS56164442A publication Critical patent/JPS56164442A/ja
Publication of JPS6239790B2 publication Critical patent/JPS6239790B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP6803380A 1980-05-22 1980-05-22 Response system between microprogram processing devices Granted JPS56164442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6803380A JPS56164442A (en) 1980-05-22 1980-05-22 Response system between microprogram processing devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6803380A JPS56164442A (en) 1980-05-22 1980-05-22 Response system between microprogram processing devices

Publications (2)

Publication Number Publication Date
JPS56164442A true JPS56164442A (en) 1981-12-17
JPS6239790B2 JPS6239790B2 (enrdf_load_stackoverflow) 1987-08-25

Family

ID=13362074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6803380A Granted JPS56164442A (en) 1980-05-22 1980-05-22 Response system between microprogram processing devices

Country Status (1)

Country Link
JP (1) JPS56164442A (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55115155A (en) * 1979-02-27 1980-09-04 Matsushita Electric Ind Co Ltd One chip multi-microcomputer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55115155A (en) * 1979-02-27 1980-09-04 Matsushita Electric Ind Co Ltd One chip multi-microcomputer

Also Published As

Publication number Publication date
JPS6239790B2 (enrdf_load_stackoverflow) 1987-08-25

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