JPS56159728A - Local bus interface unit for controlling information transfer between units in central subsystem - Google Patents

Local bus interface unit for controlling information transfer between units in central subsystem

Info

Publication number
JPS56159728A
JPS56159728A JP5575681A JP5575681A JPS56159728A JP S56159728 A JPS56159728 A JP S56159728A JP 5575681 A JP5575681 A JP 5575681A JP 5575681 A JP5575681 A JP 5575681A JP S56159728 A JPS56159728 A JP S56159728A
Authority
JP
Japan
Prior art keywords
units
interface unit
bus interface
local bus
information transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5575681A
Other languages
English (en)
Inventor
Piitaasu Aasaa
Esu Negii Birendora
Ii Kutsushingu Dabitsudo
Pii Buraun Richiyaado
Esu Jiyoisu Toomasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of JPS56159728A publication Critical patent/JPS56159728A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Complex Calculations (AREA)
JP5575681A 1980-04-15 1981-04-15 Local bus interface unit for controlling information transfer between units in central subsystem Pending JPS56159728A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/140,622 US4323967A (en) 1980-04-15 1980-04-15 Local bus interface for controlling information transfers between units in a central subsystem

Publications (1)

Publication Number Publication Date
JPS56159728A true JPS56159728A (en) 1981-12-09

Family

ID=22492071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5575681A Pending JPS56159728A (en) 1980-04-15 1981-04-15 Local bus interface unit for controlling information transfer between units in central subsystem

Country Status (8)

Country Link
US (1) US4323967A (ja)
JP (1) JPS56159728A (ja)
AU (1) AU6945981A (ja)
CA (1) CA1165456A (ja)
DE (1) DE3114934A1 (ja)
FR (1) FR2480458B1 (ja)
GB (1) GB2074765B (ja)
IT (1) IT1170892B (ja)

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US4482949A (en) * 1981-07-20 1984-11-13 Motorola, Inc. Unit for prioritizing earlier and later arriving input requests
US4604500A (en) * 1981-12-02 1986-08-05 At&T Bell Laboratories Multiprocessing interrupt arrangement
DE3382805T2 (de) * 1982-08-23 1996-09-26 Western Electric Co Rechner mit dynamischem Aufbau eines Befehlzusatzfeldes zur Speicherung der folgenden Befehlsadresse.
US4587609A (en) * 1983-07-01 1986-05-06 Honeywell Information Systems Inc. Lockout operation among asynchronous accessers of a shared computer system resource
US4633245A (en) * 1983-12-30 1986-12-30 International Business Machines Corporation Local area network interconnect switching system
DE3502147A1 (de) * 1984-01-23 1985-08-08 Hitachi Microcomputer Engineering Ltd., Kodaira, Tokio/Tokyo Datenverarbeitungssystem mit verbesserter pufferspeichersteuerung
US4941088A (en) * 1985-02-05 1990-07-10 Digital Equipment Corporation Split bus multiprocessing system with data transfer between main memory and caches using interleaving of sub-operations on sub-busses
US5101478A (en) * 1985-06-28 1992-03-31 Wang Laboratories, Inc. I/O structure for information processing system
US4791562A (en) * 1985-12-02 1988-12-13 Unisys Corporation Data processing system in which modules logically "OR" number sequences onto control lines to obtain the use of a time shared bus
US4788640A (en) * 1986-01-17 1988-11-29 Intel Corporation Priority logic system
US4727486A (en) * 1986-05-02 1988-02-23 Honeywell Information Systems Inc. Hardware demand fetch cycle system interface
NL8603193A (nl) * 1986-12-16 1988-07-18 Hollandse Signaalapparaten Bv Database-systeem.
US5091845A (en) * 1987-02-24 1992-02-25 Digital Equipment Corporation System for controlling the storage of information in a cache memory
US5029074A (en) * 1987-06-29 1991-07-02 Digital Equipment Corporation Bus adapter unit for digital processing system
US4775431A (en) * 1987-11-23 1988-10-04 Atlas Powder Company Macroemulsion for preparing high density explosive compositions
US5185879A (en) * 1988-01-21 1993-02-09 Akira Yamada Cache system and control method therefor
US5006982A (en) * 1988-10-21 1991-04-09 Siemens Ak. Method of increasing the bandwidth of a packet bus by reordering reply packets
GB2226666B (en) * 1988-12-30 1993-07-07 Intel Corp Request/response protocol
US5081609A (en) * 1989-01-10 1992-01-14 Bull Hn Information Systems Inc. Multiprocessor controller having time shared control store
JPH02226454A (ja) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> コンピユータ・システムおよびそのデータ転送方法
CA2007737C (en) * 1989-02-24 1998-04-28 Paul Samuel Gallo Data transfer operations between two asynchronous buses
EP0440456B1 (en) * 1990-01-31 1997-01-08 Hewlett-Packard Company Microprocessor burst mode with external system memory
US5678020A (en) * 1994-01-04 1997-10-14 Intel Corporation Memory subsystem wherein a single processor chip controls multiple cache memory chips
US5832534A (en) * 1994-01-04 1998-11-03 Intel Corporation Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
US5761422A (en) * 1995-03-22 1998-06-02 Telefonaktiebolaget Lm Ericsson Transferring address of data in buffer memory between processors using read-only register with respect to second processor
FR2737591B1 (fr) * 1995-08-03 1997-10-17 Sgs Thomson Microelectronics Dispositif d'organisation d'acces a un bus memoire
US6202125B1 (en) 1996-11-25 2001-03-13 Intel Corporation Processor-cache protocol using simple commands to implement a range of cache configurations
US6209072B1 (en) 1997-05-06 2001-03-27 Intel Corporation Source synchronous interface between master and slave using a deskew latch
JP5220974B2 (ja) 1999-10-14 2013-06-26 ブルアーク ユーケー リミテッド ハードウェア実行又はオペレーティングシステム機能の加速のための装置及び方法
US20020188697A1 (en) * 2001-06-08 2002-12-12 O'connor Michael A. A method of allocating storage in a storage area network
US7457822B1 (en) * 2002-11-01 2008-11-25 Bluearc Uk Limited Apparatus and method for hardware-based file system
US8041735B1 (en) 2002-11-01 2011-10-18 Bluearc Uk Limited Distributed file system and method
US20090198952A1 (en) * 2008-02-04 2009-08-06 Apple Inc Memory Mapping Architecture

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3593300A (en) * 1967-11-13 1971-07-13 Ibm Arrangement for automatically selecting units for task executions in data processing systems
US4016541A (en) * 1972-10-10 1977-04-05 Digital Equipment Corporation Memory unit for connection to central processor unit and interconnecting bus
US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit
DE2546202A1 (de) * 1975-10-15 1977-04-28 Siemens Ag Rechnersystem aus mehreren miteinander verbundenen und zusammenwirkenden einzelrechnern und verfahren zum betrieb des rechnersystems
US4067059A (en) * 1976-01-29 1978-01-03 Sperry Rand Corporation Shared direct memory access controller
US4128876A (en) * 1977-04-28 1978-12-05 International Business Machines Corporation Synchronous microcode generated interface for system of microcoded data processors
US4149242A (en) * 1977-05-06 1979-04-10 Bell Telephone Laboratories, Incorporated Data interface apparatus for multiple sequential processors
US4246637A (en) * 1978-06-26 1981-01-20 International Business Machines Corporation Data processor input/output controller
US4231086A (en) * 1978-10-31 1980-10-28 Honeywell Information Systems, Inc. Multiple CPU control system

Also Published As

Publication number Publication date
FR2480458A1 (fr) 1981-10-16
IT8148285A0 (it) 1981-04-15
IT1170892B (it) 1987-06-03
GB2074765A (en) 1981-11-04
GB2074765B (en) 1983-12-14
AU6945981A (en) 1981-10-22
CA1165456A (en) 1984-04-10
US4323967A (en) 1982-04-06
FR2480458B1 (fr) 1988-05-27
DE3114934A1 (de) 1982-03-04

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