JPS56154812A - Level stabilizer - Google Patents

Level stabilizer

Info

Publication number
JPS56154812A
JPS56154812A JP5760280A JP5760280A JPS56154812A JP S56154812 A JPS56154812 A JP S56154812A JP 5760280 A JP5760280 A JP 5760280A JP 5760280 A JP5760280 A JP 5760280A JP S56154812 A JPS56154812 A JP S56154812A
Authority
JP
Japan
Prior art keywords
output
voltage
level
sine wave
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5760280A
Other languages
Japanese (ja)
Inventor
Kiyoshi Minematsu
Shinichi Tsuchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5760280A priority Critical patent/JPS56154812A/en
Publication of JPS56154812A publication Critical patent/JPS56154812A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L5/00—Automatic control of voltage, current, or power

Landscapes

  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

PURPOSE:To improve the stability of an output level and to simplify a circuit by detecting and controlling the level of a sine wave extracted from a rectangular wave. CONSTITUTION:An input signal composed of a rectangular wave is passed through amplifying circuit AMP and filter BPF to extract the sine wave output. Part of this output is converted by diode D1 and capacitor C into the DC voltage that corresponds to the output level. Then, differential amplifying circuit D-AMP amplifies the difference between the DC voltage and reference voltage Vs and subtracts the amplified voltage from reference voltage Vs to output the difference. Thus, the output rectangular wave of AMP is amplitude-limited according to the output voltage of D-AMP. An automatic gain adjustment loop is formed as mentioned above, so the level of the sine wave output from BPF is held constant at any time even if the load fluctuates. Further, none of elements such as FET and a thermistor is required, simplifying the circuit.
JP5760280A 1980-04-30 1980-04-30 Level stabilizer Pending JPS56154812A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5760280A JPS56154812A (en) 1980-04-30 1980-04-30 Level stabilizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5760280A JPS56154812A (en) 1980-04-30 1980-04-30 Level stabilizer

Publications (1)

Publication Number Publication Date
JPS56154812A true JPS56154812A (en) 1981-11-30

Family

ID=13060395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5760280A Pending JPS56154812A (en) 1980-04-30 1980-04-30 Level stabilizer

Country Status (1)

Country Link
JP (1) JPS56154812A (en)

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