JPS5615059U - - Google Patents

Info

Publication number
JPS5615059U
JPS5615059U JP1979095327U JP9532779U JPS5615059U JP S5615059 U JPS5615059 U JP S5615059U JP 1979095327 U JP1979095327 U JP 1979095327U JP 9532779 U JP9532779 U JP 9532779U JP S5615059 U JPS5615059 U JP S5615059U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1979095327U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1979095327U priority Critical patent/JPS5615059U/ja
Priority to EP80302341A priority patent/EP0023400B1/en
Priority to DE8080302341T priority patent/DE3067129D1/de
Publication of JPS5615059U publication Critical patent/JPS5615059U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/17—Containers or parts thereof characterised by their materials
    • H10W76/18—Insulating materials, e.g. resins, glasses or ceramics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/09181—Notches in edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Combinations Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP1979095327U 1979-07-11 1979-07-11 Pending JPS5615059U (en:Method)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP1979095327U JPS5615059U (en:Method) 1979-07-11 1979-07-11
EP80302341A EP0023400B1 (en) 1979-07-11 1980-07-10 Leadless packages for semiconductor devices
DE8080302341T DE3067129D1 (en) 1979-07-11 1980-07-10 Leadless packages for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1979095327U JPS5615059U (en:Method) 1979-07-11 1979-07-11

Publications (1)

Publication Number Publication Date
JPS5615059U true JPS5615059U (en:Method) 1981-02-09

Family

ID=14134628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1979095327U Pending JPS5615059U (en:Method) 1979-07-11 1979-07-11

Country Status (3)

Country Link
EP (1) EP0023400B1 (en:Method)
JP (1) JPS5615059U (en:Method)
DE (1) DE3067129D1 (en:Method)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347457A (ja) * 2002-05-24 2003-12-05 Kyocera Corp 配線基板
JPWO2016203774A1 (ja) * 2015-06-19 2017-10-12 日本電信電話株式会社 フレキシブルプリント配線板のはんだ接合構造

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4551746A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation
GB2197540B (en) * 1986-11-12 1991-04-17 Murata Manufacturing Co A circuit structure.
DE3784906T2 (de) * 1987-01-28 1993-10-07 Unisys Corp Verfahren, das eine elastische Folie benutzt zum Herstellen einer integrierten Schaltungspackung mit Kontaktflecken in einer abgestuften Grube.
US5008492A (en) * 1989-10-20 1991-04-16 Hughes Aircraft Company High current feedthrough package
US5455385A (en) * 1993-06-28 1995-10-03 Harris Corporation Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses
TW276356B (en:Method) * 1994-06-24 1996-05-21 Ibm
JP4138211B2 (ja) * 2000-07-06 2008-08-27 株式会社村田製作所 電子部品およびその製造方法、集合電子部品、電子部品の実装構造、ならびに電子装置
KR100489820B1 (ko) * 2002-11-19 2005-05-16 삼성전기주식회사 세라믹 다층기판 및 그 제조방법
US6917265B2 (en) * 2003-05-22 2005-07-12 Synergy Microwave Corporation Microwave frequency surface mount components and methods of forming same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128829B1 (en:Method) * 1968-10-21 1976-08-21
US3801881A (en) * 1971-10-30 1974-04-02 Nippon Electric Co Packaged semiconductor device including a housing in the form of a rectangular parallelepiped and ceramic rectangular base member
JPS5116258B2 (en:Method) * 1971-10-30 1976-05-22
US3872583A (en) * 1972-07-10 1975-03-25 Amdahl Corp LSI chip package and method
JPS5524423A (en) * 1978-08-10 1980-02-21 Nissan Motor Co Ltd Semiconductor pressure sensor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347457A (ja) * 2002-05-24 2003-12-05 Kyocera Corp 配線基板
JPWO2016203774A1 (ja) * 2015-06-19 2017-10-12 日本電信電話株式会社 フレキシブルプリント配線板のはんだ接合構造

Also Published As

Publication number Publication date
EP0023400B1 (en) 1984-03-21
EP0023400A1 (en) 1981-02-04
DE3067129D1 (en) 1984-04-26

Similar Documents

Publication Publication Date Title
FR2447310B1 (en:Method)
FR2446712B1 (en:Method)
BR8002583A (en:Method)
BR8006808A (en:Method)
FR2445761B1 (en:Method)
FR2448320B1 (en:Method)
FR2446529B1 (en:Method)
FR2449367B3 (en:Method)
FR2446824B1 (en:Method)
FR2450521B3 (en:Method)
AU78390S (en:Method)
AU77669S (en:Method)
AU79826S (en:Method)
AU78385S (en:Method)
AU79557S (en:Method)
AU79200S (en:Method)
AU79950S (en:Method)
AU80228S (en:Method)
AU77763S (en:Method)
AU78271S (en:Method)
AU79559S (en:Method)
AU78386S (en:Method)
AU78391S (en:Method)
BR5901094U (en:Method)
AU79918S (en:Method)