JPS56150381A - Input circuit - Google Patents

Input circuit

Info

Publication number
JPS56150381A
JPS56150381A JP5470580A JP5470580A JPS56150381A JP S56150381 A JPS56150381 A JP S56150381A JP 5470580 A JP5470580 A JP 5470580A JP 5470580 A JP5470580 A JP 5470580A JP S56150381 A JPS56150381 A JP S56150381A
Authority
JP
Japan
Prior art keywords
point
switch
signal
inverter
signal phi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5470580A
Other languages
Japanese (ja)
Inventor
Heihachiro Ebihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP5470580A priority Critical patent/JPS56150381A/en
Publication of JPS56150381A publication Critical patent/JPS56150381A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G5/00—Setting, i.e. correcting or changing, the time-indication
    • G04G5/005—Debouncing circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE:To decrease as less as possible the number of elements and thus minimize the size of an integrated circuit, by providing a NAND circuit an inverter to form a switch circuit. CONSTITUTION:When the signal phi is set at L in an open state of the switch S, the point Y of connection is set at H. Accordingly the point X of connection is set at L. These state of points X and Y are maintained even if the signal phi is reset to H. When the switch S is closed, the point X are set forcibly at H. In this case, the point Y is set at L if the signal phi is at H. If the signal is at L, the point Y is set at H. Then the point X is set at L by the inverter 4. Here the internal resistance of inverter 4 is set larger than that of the side of switch S. As a result, the point X is logically maintained at H. The signal of a certain level emerges at the point X in accordance with the state of switch S. And the pulse-type signal synchronized with the signal phi is obtained at the point Y only when the switch S is closed.
JP5470580A 1980-04-24 1980-04-24 Input circuit Pending JPS56150381A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5470580A JPS56150381A (en) 1980-04-24 1980-04-24 Input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5470580A JPS56150381A (en) 1980-04-24 1980-04-24 Input circuit

Publications (1)

Publication Number Publication Date
JPS56150381A true JPS56150381A (en) 1981-11-20

Family

ID=12978206

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5470580A Pending JPS56150381A (en) 1980-04-24 1980-04-24 Input circuit

Country Status (1)

Country Link
JP (1) JPS56150381A (en)

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