JPS56149145A - Automatic forming circuit for return loop - Google Patents

Automatic forming circuit for return loop

Info

Publication number
JPS56149145A
JPS56149145A JP5267280A JP5267280A JPS56149145A JP S56149145 A JPS56149145 A JP S56149145A JP 5267280 A JP5267280 A JP 5267280A JP 5267280 A JP5267280 A JP 5267280A JP S56149145 A JPS56149145 A JP S56149145A
Authority
JP
Japan
Prior art keywords
signal
circuits
communication
circuit
subscriber circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5267280A
Other languages
Japanese (ja)
Other versions
JPS639706B2 (en
Inventor
Takashi Akao
Tadashi Yatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP5267280A priority Critical patent/JPS56149145A/en
Publication of JPS56149145A publication Critical patent/JPS56149145A/en
Publication of JPS639706B2 publication Critical patent/JPS639706B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To maintain the transmission quality of a subscriber circuit without spoiling communication service, by providing a means capable of discriminating a signal arriving from the subscriber circuit and by closing or opening a return loop to the subscriber circuit according to whether the signal indicates a no-communication state or a request for communication. CONSTITUTION:Between data switching equipment SW and terminal equipment T, an automatic forming circuit for a return loop is provided which has delay circuits 2 and 12, selecting circuits 1 and 9, and path LP. This circuit is provided with no- communication state detecting circuits 3 and 5 and communication-request signal detecting circuits 5 and 6 which discriminate signals from signal line Df from equipment T and signal line Ef of equipment SW, and outputs of circuits 3 and 5, and 5 and 6 are applied to FF circuits 8 and 9 via gates 12 and 13, and 14. Then, a signal from a subscriber circuit is detected by circuits 3 and 5, and 5 and 6 to close the automatic forming circuit for the loop when the signal indicates a no-communication state or to open it when the signal is a communication request signal, so that the quality of the subscriber circuit will be maintained without spoiling the communication service.
JP5267280A 1980-04-21 1980-04-21 Automatic forming circuit for return loop Granted JPS56149145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5267280A JPS56149145A (en) 1980-04-21 1980-04-21 Automatic forming circuit for return loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5267280A JPS56149145A (en) 1980-04-21 1980-04-21 Automatic forming circuit for return loop

Publications (2)

Publication Number Publication Date
JPS56149145A true JPS56149145A (en) 1981-11-18
JPS639706B2 JPS639706B2 (en) 1988-03-01

Family

ID=12921355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5267280A Granted JPS56149145A (en) 1980-04-21 1980-04-21 Automatic forming circuit for return loop

Country Status (1)

Country Link
JP (1) JPS56149145A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01139306U (en) * 1988-03-16 1989-09-22
JPH01139305U (en) * 1988-03-16 1989-09-22

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516570A (en) * 1978-07-21 1980-02-05 Nec Corp Subscribersigma return circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516570A (en) * 1978-07-21 1980-02-05 Nec Corp Subscribersigma return circuit

Also Published As

Publication number Publication date
JPS639706B2 (en) 1988-03-01

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