JPS5614772A - Signal processing system - Google Patents

Signal processing system

Info

Publication number
JPS5614772A
JPS5614772A JP9001779A JP9001779A JPS5614772A JP S5614772 A JPS5614772 A JP S5614772A JP 9001779 A JP9001779 A JP 9001779A JP 9001779 A JP9001779 A JP 9001779A JP S5614772 A JPS5614772 A JP S5614772A
Authority
JP
Japan
Prior art keywords
output
signal
period
input
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9001779A
Other languages
Japanese (ja)
Inventor
Tsuneo Imai
Akira Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Toshiba Corp
Nippon Telegraph and Telephone Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Nippon Telegraph and Telephone Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9001779A priority Critical patent/JPS5614772A/en
Publication of JPS5614772A publication Critical patent/JPS5614772A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40—Picture signal circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimile Image Signal Circuits (AREA)

Abstract

PURPOSE:To make it possible to obtain an output by secure sampling without overlooking not only thin level ''1'' but also level ''0'' by obtaining an output signal by checking an input signal throughout one sampling period. CONSTITUTION:Binary input signal (a) is input to input terminal 1 and applied to ''1''-level detection part 8 and change detection part 10 and sampling clock (b), on the other hand, is input to input terminal 2. When signal (a) changes ''0''-''1'' in one sampling period, detection output (d) of detection part 8 is ''1'' and when output (j) of output signal memory part 15 one period before is ''0'', output (h) is ''1'' and output (g) of logic conversion part 13 is ''1'', which is stored in memory part 15. This is output from terminal 16 in the next period. Further, when signal (a) changes from ''1''-''0'', ''0'' is output from terminal 16 in the next period. On the other hand, when signal (a) does not change in one period, output (e) of detection part 8 is ''1'' and level ''1'' or ''0'' of signal (a) is output from terminal 16, as it is, in the next period.
JP9001779A 1979-07-16 1979-07-16 Signal processing system Pending JPS5614772A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9001779A JPS5614772A (en) 1979-07-16 1979-07-16 Signal processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9001779A JPS5614772A (en) 1979-07-16 1979-07-16 Signal processing system

Publications (1)

Publication Number Publication Date
JPS5614772A true JPS5614772A (en) 1981-02-13

Family

ID=13986931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9001779A Pending JPS5614772A (en) 1979-07-16 1979-07-16 Signal processing system

Country Status (1)

Country Link
JP (1) JPS5614772A (en)

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