JPS56143064A - Memory device - Google Patents

Abstract

PURPOSE:To enable to response quickly with the access exclusively from one set of request device, by providing the device with the priority access control circuit inputting the priority signal from a plurality of memory access request devices. CONSTITUTION:If the priority signal 31 is output from CPU 1 and the priority signal 32 is not output from CPU2, and AND gate 6a is open and the AND gate 7a is closed, and the access request only from CPU1 is received. The address signal, data signal and command signal from CPU1 are stably transmitted to the memory cell 15 via the AND gate 19 and OR gate 21. Further, since the AND circuit 25 is open and the AND circuit 26 is closed, input is directly made to FF14 not through the delay circuit 13, allowing to transmit the start signal to the memory cell 15 instantly to the access request from CPU1. Further, the signals 31, 32 are both at logic 0, the start signal to the memory cell 15 passes through the delay circuit 13 and starts the memory with delay.