JPS56140745A - Forming method of circuit test system - Google Patents

Forming method of circuit test system

Info

Publication number
JPS56140745A
JPS56140745A JP4419680A JP4419680A JPS56140745A JP S56140745 A JPS56140745 A JP S56140745A JP 4419680 A JP4419680 A JP 4419680A JP 4419680 A JP4419680 A JP 4419680A JP S56140745 A JPS56140745 A JP S56140745A
Authority
JP
Japan
Prior art keywords
circuit
teleprinter
circuit test
board
test system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4419680A
Other languages
Japanese (ja)
Inventor
Akira Onodera
Ryoji Takano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4419680A priority Critical patent/JPS56140745A/en
Publication of JPS56140745A publication Critical patent/JPS56140745A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements

Abstract

PURPOSE:To improve the economic property without impairing the benefit of operation, by storing a tie circuit into the circuit test system comprising plural circuit test boards and then connecting exclusively the teleprinter of each circuit test board to the tie circuit. CONSTITUTION:A tie circuit 8 is stored in the circuit test system 3' comprising the circuit test boards 4-1-4-n. The teleprinter 5-1 incorporated in the prescribed test board 4-1 is switched to be connected to the circuit 8 at all times in case the teleprinter 5-1 is not connected to the board 4-1 in order to prepare for the connection given from the subscriber telegraph switchboard 1. Thus a connection is inhibited for other teleprinters 5-2-5-n. Either one of the teleprinters 5-2-5-n can be connected exclusively to the circuit 8 while the teleprinter 5-1 is connected to the board 4-1. In case no connection is given to any teleprinter, the circuit 8 is connected to the block signal transmitting circuit. Thus the circuit 8 is blocked.
JP4419680A 1980-04-04 1980-04-04 Forming method of circuit test system Pending JPS56140745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4419680A JPS56140745A (en) 1980-04-04 1980-04-04 Forming method of circuit test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4419680A JPS56140745A (en) 1980-04-04 1980-04-04 Forming method of circuit test system

Publications (1)

Publication Number Publication Date
JPS56140745A true JPS56140745A (en) 1981-11-04

Family

ID=12684814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4419680A Pending JPS56140745A (en) 1980-04-04 1980-04-04 Forming method of circuit test system

Country Status (1)

Country Link
JP (1) JPS56140745A (en)

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